2-mem.pptx - EEL 6764 Principles of Computer Architecture...

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EEL 6764 Principles of Computer Architecture Memory Hierarchy Design Instructor: Hao Zheng Department of Computer Science & Engineering University of South Florida Tampa, FL 33620 Email: [email protected] Phone: (813)974-4757 Fax: (813)974-5456 1
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A Simplified View of Computers CPU Interconnect HD DISP KB Cache Memory ...
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Reading Computer Architecture: A Quantitative Approach Chapter 2, Appendix B Computer Organization and Design: The Hardware/Software Interface Chapter 5 3
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Memory Technology – Overview o Static RAM (SRAM) 0.5ns – 2ns, $2000 – $5000 per GB o Dynamic RAM (DRAM) 20ns – 30ns, $10 – $50 per GB o Magnetic disk 5ms – 20ms, $0.20 – $2 per GB o Ideal memory Access time of SRAM Capacity and cost/GB of disk 4
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The “Memory Wall” 5 Processor mem accesses/sec vs DRAM accesses/sec 2.1 Introduction
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The “Memory Wall” – A Multi-Core Case Aggregate peak bandwidth grows with # cores: Intel Core i7 can generate two references per core per clock Four cores and 3.2 GHz clock 25.6 billion 64-bit data references/second + 12.8 billion 128-bit instruction references = 409.6 GB/s! DRAM bandwidth is only 6% of this (25 GB/s) Requires: Multi-port, pipelined caches Two levels of cache per core Shared third-level cache on chip 6 2.1 Introduction
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Principle of Locality – Review o Programs often access a small proportion of their address space at any time o Temporal locality Items accessed recently are likely to be accessed again soon e.g., instructions in a loop, induction variables o Spatial locality Items near those accessed recently are likely to be accessed soon E.g., sequential instruction access, array data 7 B.1 Introduction
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Principle of Locality – Review o Identify Temporal and spatial locality 8 int sum = 0; int x[1000]; for (int c = 0; c < 1000; c++) { sum += x[c]; x[c] = 0; } B.1 Introduction
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Memory Hierarchy o Programmers want unlimited amounts of memory with low latency o Fast memory technology is more expensive per bit than slower memory o Solution: organize memory system into a hierarchy Entire addressable memory space available in largest, slowest memory Incrementally smaller and faster memories, each containing a subset of the memory below it, proceed in steps up toward the processor o Temporal and spatial locality insures that nearly all references can be found in smaller memories Gives the illusion of a large, fast memory being presented to the processor 9 2.1 Introduction
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Memory Hierarchy 10 2.1 Introduction
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Energy Consumptions Figure 1: Energy table for 45nm CMOS process. Memory access is 2-3 orders of magnitude more energy expensive than arithmetic operations. O p e r a t i o n E n e r g y [ p J ] R e l a t i v e C o s t 3 2 b i t i n t A D D 0 . 1 1 3 2 b i t fl o a t A D D 0 . 9 9 3 2 b i t R e g i s t e r F i l e 1 1 0 3 2 b i t i n t M U L T 3 . 1 3 1 3 2 b i t fl o a t M U L T 3 . 7 3 7 3 2 b i t S R A M C a c h e 5 5 0 3 2 b i t D R A M M e m o r y 6 4 0 6 4 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 R e l a t i v e E n e r g y C o s t Song Han, FPGA’17 talk, “Deep Learning
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