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Unformatted text preview: Product Folder Order Now Technical Documents Tools & Software Support & Community TMS320F28379D, TMS320F28377D TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880I – DECEMBER 2013 – REVISED MARCH 2018 TMS320F2837xD Dual-Core Delfino™ Microcontrollers 1 Device Overview 1.1 Features 1 • Dual-Core Architecture – Two TMS320C28x 32-Bit CPUs – 200 MHz – IEEE 754 Single-Precision Floating-Point Unit (FPU) – Trigonometric Math Unit (TMU) – Viterbi/Complex Math Unit (VCU-II) • Two Programmable Control Law Accelerators (CLAs) – 200 MHz – IEEE 754 Single-Precision Floating-Point Instructions – Executes Code Independently of Main CPU • On-Chip Memory – 512KB (256KW) or 1MB (512KW) of Flash (ECC-Protected) – 172KB (86KW) or 204KB (102KW) of RAM (ECC-Protected or Parity-Protected) – Dual-Zone Security Supporting Third-Party Development – Unique Identification Number • Clock and System Control – Two Internal Zero-Pin 10-MHz Oscillators – On-Chip Crystal Oscillator – Windowed Watchdog Timer Module – Missing Clock Detection Circuitry • 1.2-V Core, 3.3-V I/O Design • System Peripherals – Two External Memory Interfaces (EMIFs) With ASRAM and SDRAM Support – Dual 6-Channel Direct Memory Access (DMA) Controllers – Up to 169 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins With Input Filtering – Expanded Peripheral Interrupt Controller (ePIE) – Multiple Low-Power Mode (LPM) Support With External Wakeup • Communications Peripherals – USB 2.0 (MAC + PHY) – Support for 12-Pin 3.3 V-Compatible Universal Parallel Port (uPP) Interface – Two Controller Area Network (CAN) Modules (Pin-Bootable) – Three High-Speed (up to 50-MHz) SPI Ports (Pin-Bootable) – Two Multichannel Buffered Serial Ports (McBSPs) – Four Serial Communications Interfaces (SCI/UART) (Pin-Bootable) – Two I2C Interfaces (Pin-Bootable) • Analog Subsystem – Up to Four Analog-to-Digital Converters (ADCs) – 16-Bit Mode – 1.1 MSPS Each (up to 4.4-MSPS System Throughput) – Differential Inputs – Up to 12 External Channels – 12-Bit Mode – 3.5 MSPS Each (up to 14-MSPS System Throughput) – Single-Ended Inputs – Up to 24 External Channels – Single Sample-and-Hold (S/H) on Each ADC – Hardware-Integrated Post-Processing of ADC Conversions – Saturating Offset Calibration – Error From Setpoint Calculation – High, Low, and Zero-Crossing Compare, With Interrupt Capability – Trigger-to-Sample Delay Capture – Eight Windowed Comparators With 12-Bit Digital-to-Analog Converter (DAC) References – Three 12-Bit Buffered DAC Outputs • Enhanced Control Peripherals – 24 Pulse Width Modulator (PWM) Channels With Enhanced Features – 16 High-Resolution Pulse Width Modulator (HRPWM) Channels – High Resolution on Both A and B Channels of 8 PWM Modules – Dead-Band Support (on Both Standard and High Resolution) – Six Enhanced Capture (eCAP) Modules – Three Enhanced Quadrature Encoder Pulse (eQEP) Modules – Eight Sigma-Delta Filter Module (SDFM) Input Channels, 2 Parallel Filters per Channel – Standard SDFM Data Filtering – Comparator Filter for Fast Action for Out of Range 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TMS320F28379D, TMS320F28377D TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880I – DECEMBER 2013 – REVISED MARCH 2018 • Configurable Logic Block (CLB) – Augments Existing Peripheral Capability – Supports Position Manager Solutions • Package Options: – Lead-Free, Green Packaging – 337-Ball New Fine Pitch Ball Grid Array (nFBGA) [ZWT Suffix] – 176-Pin PowerPAD™ Thermally Enhanced LowProfile Quad Flatpack (HLQFP) [PTP Suffix] – 100-Pin PowerPAD Thermally Enhanced Thin Quad Flatpack (HTQFP) [PZP Suffix] 1.2 • • • • • • • Temperature Options: – T: –40ºC to 105ºC Junction – S: –40ºC to 125ºC Junction – Q: –40ºC to 125ºC Free-Air (AEC Q100 Qualification for Automotive Applications) Applications Advanced Driver Assistance Systems (ADAS) Building Automation Electronic Point of Sale Electric Vehicle/Hybrid Electric Vehicle (EV/HEV) Powertrain Factory Automation Grid Infrastructure 1.3 • • • • • • Industrial Transport Medical, Healthcare, and Fitness Motor Drives Power Delivery Telecom Infrastructure Test and Measurement Description The Delfino™ TMS320F2837xD is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced closed-loop control applications such as industrial drives and servo motor control; solar inverters and converters; digital power; transportation; and power line communications. Complete development packages for digital power and industrial drives are available as part of the powerSUITE and DesignDRIVE initiatives. While the Delfino product line is not new to the TMS320C2000™ portfolio, the F2837xD supports a new dual-core C28x architecture that significantly boosts system performance. The integrated analog and control peripherals also let designers consolidate control architectures and eliminate multiprocessor use in high-end systems. The dual real-time control subsystems are based on TI’s 32-bit C28x floating-point CPUs, which provide 200 MHz of signal processing performance in each core. The C28x CPUs are further boosted by the new TMU accelerator, which enables fast execution of algorithms with trigonometric operations common in transforms and torque loop calculations; and the VCU accelerator, which reduces the time for complex math operations common in encoded applications. The F2837xD microcontroller family features two CLA real-time control coprocessors. The CLA is an independent 32-bit floating-point processor that runs at the same speed as the main CPU. The CLA responds to peripheral triggers and executes code concurrently with the main C28x CPU. This parallel processing capability can effectively double the computational performance of a real-time control system. By using the CLA to service time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and diagnostics. The dual C28x+CLA architecture enables intelligent partitioning between various system tasks. For example, one C28x+CLA core can be used to track speed and position, while the other C28x+CLA core can be used to control torque and current loops. The TMS320F2837xD supports up to 1MB (512KW) of onboard flash memory with error correction code (ECC) and up to 204KB (102KW) of SRAM. Two 128-bit secure zones are also available on each CPU for code protection. 2 Device Overview Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28379D TMS320F28377D TMS320F28376D TMS320F28375D TMS320F28374D TMS320F28379D, TMS320F28377D TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880I – DECEMBER 2013 – REVISED MARCH 2018 Performance analog and control peripherals are also integrated on the F2837xD MCU to further enable system consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple analog signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM) works in conjunction with the sigma-delta modulator to enable isolated current shunt measurements. The Comparator Subsystem (CMPSS) with windowed comparators allows for protection of power stages when current limit conditions are exceeded or not met. Other analog and control peripherals include DACs, PWMs, eCAPs, eQEPs, and other peripherals. Peripherals such as EMIFs, CAN modules (ISO 11898-1/CAN 2.0B-compliant), and a new uPP interface extend the connectivity of the F2837xD. The uPP interface is a new feature of the C2000™ MCUs and supports high-speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly, a USB 2.0 port with MAC and PHY lets users easily add universal serial bus (USB) connectivity to their application. Device Information (1) PACKAGE BODY SIZE TMS320F28379DZWT PART NUMBER nFBGA (337) 16.0 mm × 16.0 mm TMS320F28377DZWT nFBGA (337) 16.0 mm × 16.0 mm TMS320F28376DZWT nFBGA (337) 16.0 mm × 16.0 mm TMS320F28375DZWT nFBGA (337) 16.0 mm × 16.0 mm TMS320F28374DZWT nFBGA (337) 16.0 mm × 16.0 mm TMS320F28379DPTP HLQFP (176) 24.0 mm × 24.0 mm TMS320F28377DPTP HLQFP (176) 24.0 mm × 24.0 mm TMS320F28376DPTP HLQFP (176) 24.0 mm × 24.0 mm TMS320F28375DPTP HLQFP (176) 24.0 mm × 24.0 mm TMS320F28374DPTP HLQFP (176) 24.0 mm × 24.0 mm TMS320F28375DPZP HTQFP (100) 14.0 mm × 14.0 mm (1) For more information on these devices, see Mechanical, Packaging, and Orderable Information. Device Overview Submit Documentation Feedback Product Folder Links: TMS320F28379D TMS320F28377D TMS320F28376D TMS320F28375D TMS320F28374D Copyright © 2013–2018, Texas Instruments Incorporated 3 TMS320F28379D, TMS320F28377D TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880I – DECEMBER 2013 – REVISED MARCH 2018 1.4 Functional Block Diagram Figure 1-1 shows the CPU system and associated peripherals. PSWD Dual Code Security Module + Emulation Code Security Logic (ECSL) Secure Memories shown in Red User Configurable DCSM OTP 1K x 16 User Configurable DCSM PSWD OTP 1K x 16 FLASH FLASH 256K x 16 Secure 256K x 16 Secure PUMP Dual Code Security Module + Emulation Code Security Logic (ECSL) CPU2.CLA1 OTP/Flash Wrapper OTP/Flash Wrapper MEMCPU1 MEMCPU2 CPU1.M0 RAM 1Kx16 CPU1.CLA1 to CPU1 128x16 MSG RAM CPU1 to CPU1.CLA1 128x16 MSG RAM C28 CPU-1 CPU1.M1 RAM 1Kx16 C28 CPU-2 FPU VCU-II TMU CPU2.M0 RAM 1Kx16 FPU VCU-II TMU CPU2.M1 RAM 1Kx16 CPU1 Local Shared 6x 2Kx16 LS0-LS5 RAMs CPU1.D1 RAM 2Kx16 WD Timer NMI-WDT CPU1.CLA1 Data ROM (4Kx16) 16-/12-bit ADC x4 A5:0 A B ADC Result Regs D Config D5:0 ADCIN14 ADCIN15 Data Bus Bridge Comparator DAC Subsystem x3 (CMPSS) External Crystal or Oscillator Secure-ROM 32Kx16 Secure Aux PLL AUXCLKIN Boot-ROM 32Kx16 Nonsecure ePIE (up to 192 interrupts) TRST TCK CPU2.DMA JTAG TDI TMS TDO GPIO GPIOn EMIF2 EM2Dx EMIF1 EM2Ax Data Bus Bridge EM2CTLx Data Bus Bridge EM1CTLx UPPAST UPPACLK UPPAEN MFSXx MFSRx UPPAWT RAM uPP UPPAD[7:0] MCLKXx MCLKRx MDXx MRXx SPISTEx SPICLKx SPISIMOx SPISOMIx McBSPA/B Data Bus Bridge EM1Dx SPIA/B/C (16L FIFO) Peripheral Frame 2 EM1Ax CANA/B (32-MBOX) CANTXx USB Ctrl / PHY CANRXx SDAx SCITXDx SDx_Cy SDx_Dy EQEPxI EQEPxS I2C-A/B (16L FIFO) Data Bus Bridge USBDP SCIA/B/C/D (16L FIFO) SCLx SDFM-1/2 Data Bus Bridge USBDM Data Bus Bridge eQEP-1/2/3 EQEPxB ECAPx eCAP1/../6 EXTSYNCOUT EPWMxB EXTSYNCIN EPWMxA TZ1-TZ6 CPU Timer 0 CPU Timer 1 CPU Timer 2 CPU2 to CPU1 1Kx16 MSG RAM INTOSC2 CPU2.CLA1 Data ROM (4Kx16) CPU2 Buses EQEPxA ePWM-1/../12 Main PLL CPU2.D1 RAM 2Kx16 WD Timer NMI-WDT CPU1 Buses Peripheral Frame 1 HRPWM-1/../8 (CPU1 only) (up to 192 interrupts) INTOSC1 CPU2.D0 RAM 2Kx16 CPU1 to CPU2 1Kx16 MSG RAM ePIE CPU1.DMA SCIRXDx Analog MUX C5:2 C Boot-ROM 32Kx16 Nonsecure CPU1.CLA1 Bus B5:0 Watchdog 1/2 CPU2 Local Shared 6x 2Kx16 LS0-LS5 RAMs Global Shared 16x 4Kx16 GS0-GS15 RAMs CPU Timer 0 CPU Timer 1 CPU Timer 2 Secure-ROM 32Kx16 Secure GPIO MUX CPU2.CLA1 to CPU2 128x16 MSG RAM Interprocessor Communication (IPC) Module CPU1.D0 RAM 2Kx16 Low-Power Mode Control CPU2 to CPU2.CLA1 128x16 MSG RAM CPU2.CLA1 Bus CPU1.CLA1 GPIO MUX, Input X-BAR, Output X-BAR Copyright © 2017, Texas Instruments Incorporated Figure 1-1. Functional Block Diagram 4 Device Overview Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28379D TMS320F28377D TMS320F28376D TMS320F28375D TMS320F28374D TMS320F28379D, TMS320F28377D TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880I – DECEMBER 2013 – REVISED MARCH 2018 Table of Contents 1 Device Overview ......................................... 1 6.3 Memory 1.1 Features .............................................. 1 6.4 Identification........................................ 185 1.2 Applications ........................................... 2 6.5 Bus Architecture – Peripheral Connectivity ........ 186 1.3 Description ............................................ 2 6.6 C28x Processor .................................... 187 ........................... 4 Revision History ......................................... 6 Device Comparison ..................................... 7 3.1 Related Products ..................................... 9 Terminal Configuration and Functions ............ 10 4.1 Pin Diagrams ........................................ 10 4.2 Signal Descriptions .................................. 17 4.3 Pins With Internal Pullup and Pulldown ............. 40 4.4 Pin Multiplexing...................................... 41 4.5 Connections for Unused Pins ....................... 48 Specifications ........................................... 49 5.1 Absolute Maximum Ratings ........................ 49 5.2 ESD Ratings – Commercial ......................... 50 5.3 ESD Ratings – Automotive .......................... 50 5.4 Recommended Operating Conditions ............... 51 5.5 Power Consumption Summary ...................... 52 5.6 Electrical Characteristics ............................ 56 5.7 Thermal Resistance Characteristics ................ 57 5.8 System .............................................. 59 5.9 Analog Peripherals .................................. 95 5.10 Control Peripherals ................................ 122 5.11 Communications Peripherals ...................... 139 Detailed Description.................................. 175 6.1 Overview ........................................... 175 6.2 Functional Block Diagram ......................... 175 6.7 Control Law Accelerator ........................... 190 6.8 Direct Memory Access ............................. 191 1.4 2 3 4 5 6 Functional Block Diagram 7 8 9 ............................................ 6.9 Interprocessor Communication Module............ 193 6.10 Boot ROM and Peripheral Booting................. 194 6.11 Dual Code Security Module 6.12 6.13 Timers .............................................. 197 Nonmaskable Interrupt With Watchdog Timer (NMIWD) ........................................... 197 ....................... .......................................... ................... Applications, Implementation, and Layout ...... 7.1 TI Design or Reference Design .................... Device and Documentation Support .............. 197 6.14 Watchdog 198 6.15 Configurable Logic Block (CLB) 198 199 199 200 8.1 Device and Development Support Tool Nomenclature ...................................... 200 8.2 Tools and Software ................................ 201 8.3 Documentation Support ............................ 203 8.4 Related Links 8.5 Community Resources............................. 204 8.6 Trademarks ........................................ 204 8.7 Electrostatic Discharge Caution 8.8 Glossary............................................ 204 ...................................... ................... 204 204 Mechanical, Packaging, and Orderable Information ............................................. 205 9.1 Packaging Information ............................. 205 Table of Contents Submit Documentation Feedback Product Folder Links: TMS320F28379D TMS320F28377D TMS320F28376D TMS320F28375D TMS320F28374D Copyright © 2013–2018, Texas Instruments Incorporated 177 5 TMS320F28379D, TMS320F28377D TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880I – DECEMBER 2013 – REVISED MARCH 2018 2 Revision History Changes from July 25, 2017 to March 14, 2018 (from H Revision (July 2017) to I Revision) • • • • • • • • • • • • • • • • • • • • • • • • 6 Page Global: Globally removed TMS320F28378D. .................................................................................... 1 Section 1.1 (Features): Added "Unique Identification Number" feature........................................................ 1 Section 1.1: Added "Configurable Logic Block (CLB)" feature. ................................................................. 1 Table 3-1 (Device Comparison): Changed Conversion Time for ADC 12-bit mode from 290 ns to 280 ns. ............. 7 Table 5-1 (Device Current Consumption at 200-MHz SYSCLK): Changed "Operational (RAM)" to "Operational". Updated IDD MAX values. Added footnote about brownout events. ......................................................... 52 Section 5.6 (Electrical Characteristics): Added VHYSTERESIS. ................................................................... 56 Table 5-11 (PLL Lock Times): Updated footnote. .............................................................................. 64 Table 5-20 (Flash Parameters): Changed "Erase Time at 50k cycles" to "Erase Time at 20k cycles". ................. 69 Section 5.9 (Analog Peripherals): Updated list of analog subsystem features. ............................................ 95 Section 5.9.1.1 (ADC Configurability): Added section. ....................................................................... 100 Table 5-42 (ADC Operating Conditions (16-Bit Differential Mode)): Added footnote about VREFCM requirements. ... 102 Section 5.9.1.2.2 (ADC Timing Diagrams): Updated section. ............................................................... 108 Table 5-50 (ADC Timing Parameters): Added table. ......................................................................... 108 Figure 5-49 (ePWM Submodules and Critical Internal Signal Interconnects): Updated figure. ......................... 126 Section 5.11.2.1 (I2C Electrical Data and Timing): Added NOTE about meeting I2C protocol timing specifications. 142 Table 5-72 (McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)): Updated table title. ........................................................................................................................... 148 Table 5-74 (McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)): Updated table title. ........................................................................................................................... 149 Table 5-76 (McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)): Updated table title. ............................................................................................................................ 150 Table 5-78 (McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)): Updated table title. ........................................................................................................................... 151 Section 5.11.6 (Universal Serial Bus (USB) Controller): Updated list of USB module features. ....................... 168 Table 6-9 (Device Identification Registers): Changed UID_UNIQUE from "0x0007 03C0" to "0x0007 03CC". ....... 185 Figure 6-5 (Windowed Watchdog): Updated figure. .......................................................................... 198 Section 8.2 (Tools and Software): Added "Models" section. ................................................................ 201 Section 8.3 (Documentation Support): Updated section. .................................................................... 203 Revision History Copyright © 2013–2018, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28379D TMS320F28377D TMS320F28376D TMS320F28375D TMS320F28374D TMS320F28379D, TMS320F28377D TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880I – DECEMBER 2013 – REVISED MARCH 2018 3 Device Comparison Table 3-1 lists the features of each 2837xD device. Table 3-1. Device Comparison FEATURE (1) Package Type (ZWT is an nFBGA package. PTP is an HLQFP package. PZP is an HTQFP package.) 28379D 337-Ball ZWT 28377D 176-Pin PTP 337-Ball ZWT 28376D 176-Pin PTP 337-Ball ZWT 28375D 176-Pin PTP 337-Ball ZWT 176-Pin PTP 28374D 100-Pin PZP 337-Ball ZWT 176-Pin PTP Processor and Accelerators Number C28x 2 Frequency (MHz) 200 Floating-Point Unit (FPU) Yes VCU-II Yes TMU – Type 0 Yes Numbe...
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