16.16 Repeat Exercise 16.4 for an SRAM fabricated in a 0.25-um CMOS p.docx - 16.16 Repeat Exercise 16.4 for an SRAM fabricated in a 0.25-um CMOS

# 16.16 Repeat Exercise 16.4 for an SRAM fabricated in a 0.25-um CMOS p.docx

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16.16 Repeat Exercise 16.4 for an SRAM fabricated in a 0.25-um CMOS process for which Vpp = 2.5 V and V, = 0.5 V. EXERCISE 16.4 Find the maximum allowable WIL for the access transistors of the SRAM cell in Fig. 16.12 so that in a read operation, the voltages at Q and Q do not change by more than V. Assume that the SRAM is fabricated in a 0.18- um technology for which Vpp = 1.8 V, V = v =0.5 V and that (WIL), = 1.5. Ans. (WIL), < 2.5 Having determined the constraint imposed by the read operation on the WIL ratios of the access transistors, we now return to the circuit in Fig. 16.13, and show in Fig. 16.15 the voltage waveforms at various nodes during a read-1 operation. Observe that as we have already discussed, varises from zero to a voltage V V . Correspondingly, the change in v will be very small, justifying the assumption implicit in the analysis above that v, remains constant at Vpp. Most important, note that the voltage of the Bline, vs, decreases by a small amount AV.

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