assignment2.pdf - Mechtron 3TB4 Embedded Systems Design II Assignment 2 Due In class on Wednesday Q.1[3 4 3=10 a Consider the following code written in

assignment2.pdf - Mechtron 3TB4 Embedded Systems Design II...

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Mechtron 3TB4: Embedded Systems Design II Assignment 2 Due: In class on Wednesday February 28, 2018. Q.1 [3+4+3=10] a) Consider the following code written in Verilog HDL: module test(a, result); output [15:0] a; // 16-bit output output [31:0] result; // 32-bit output assign a= {4{4’b0101}}; assign result = {{16{a[15]}}, {a[15:0]}}; endmodule What are the values assigned to: result[25] and result[2]? b) The schematic below shows three devices attached to a bus through tri- state buffers. Given the table with input signals, specify the state that you expect to see on the bus. You can enter one of the following values: 0, 1, Z (high impedance), or SC (for short circuit). Figure 1: c) An analog signal of frequency 7kHz is sampled with a sampling rate of 4kHz. What aliasing frequency will result in the sampled data because of this sampling scheme? Show your work. 1
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Q.2 [4+6] 1. Given a digital filter’s output in the figure 2, and sampling frequency of 40kHz, calculate (approximately) the filter’s output y ( t ) for the following input signal [4] x ( t ) = 0 . 5 * sin (2 * π * 2000 * t ) + 0 . 3 * cos (2 * π * 3000 * t ) Figure 2: 2. You are given the FIR filter shown in figure 3, and set of coefficients h 0 = 1 , h 1 = 0 , h 2 = 0 . 25 , h 3 = 0 . 5
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  • Aliasing, Central processing unit, Processor register, downcounter

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