iddq.pdf - Digital Test Methods IDDQ TUTORIAL 13 IDDQ TUTORIAL Goals To show how a quiescent current supply test Iddq contributes to IC defect isolation

iddq.pdf - Digital Test Methods IDDQ TUTORIAL 13 IDDQ...

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Copyright (c) 1996,1997 T.T.T., Inc. <; 13-1 IDDQ TUTORIAL 13 Digital Test Methods IDDQ TUTORIAL Goals: To show how a quiescent current supply test, Iddq, contributes to IC defect isolation. To understand the challenges of the Iddq measurement. To select from the available Iddq test methods, the ones which most practically reduce test time. To Identify and validate circuit defect using failures analysis techniques and relate Iddq anomalies to the circuit flaw cause. Objectives: List the circuit requirements and test conditions for Iddq and describe how Iddq limit is derived. Write the advantages and disadvantages of the three main categories of electrical tests DC, Function Iddq and AC in isolating defects. List the order of defect types and their related symptoms and the characteristics of a valid Iddq failure. Topics: Iddq Concepts Defects and Faults Iddq Test Pattern Generation Testing Methods Failure Analysis Review Questions
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IDDQ TUTORIAL 13-2 Copyright (c) 1996,1997 T.T.T., Inc. <; 13 Digital Test Methods Iddq Concepts 13.0Introduction CMOS IC makers were frustrated, because, oddly, some parts which were successfully tested failed to function in the field, while some other parts suffered performance degradation. Two peculiarities were common to these escape (bad) parts: (1) Iddq is several order of magnitude higher than the normal expected residual value of less than 1uA. (2) Iddq value varies with the applied pattern between normal to abnormal. A circuit defect, such as a short or partial transistor saturation, was suspected since CMOS is a nanowatt logic. See the example below for explanation of such case where a defective device eludes screening. 13.1 Example An embedded inverter is shown in Figure 13.1 in which the source and drain of the p-FET are shorted. Ans (1): When an input logic 0 pattern is applied at A, the n-FET is turned off and the voltage appearing at the output correspond to logic 1. The value of Iddq is residual despite the existence of the short. Figure 13.1 Embedded Inverter with source to drain defect Vdd Iddq p n Input logic more logic 1 0 1 0 s d A V o primary outputs
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IDDQ TUTORIAL 13 Digital Test Methods
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