ps2.pdf - Columbia University Department of Electrical Engineering EE E4321 Problem Set#2 Learning schematic capture and circuit simulation Due October

ps2.pdf - Columbia University Department of Electrical...

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Columbia University Department of Electrical Engineering EE E4321. Problem Set #2. Learning schematic capture and circuit simulation. Due: October 2, 2019, 5 PM by electronic submission (see below) Please carefully follow these instructions. All problem sets should be submit- ted electronically as a single PDF file attachment through Courseworks. If you do your calculations with pencil and paper, please scan your work to submit it electronically. Before beginning this problem set, you must complete the on-line tutorials on Cadence’s Virtuoso Schematic Entry and Spectre simulation through the Analog Design Environment. In all of these problems, you will be using FETs in the IBM 90-nm technology and performing your analysis with Spectre on a schematic entered with Cadence Virtuoso. When you first get a set of models for a new technology, you will want to run a set of simulations to get a good “feel” for the devices. One of the first things you want
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