sheet9_sol.pdf - Faculty of Information Engineer Technology Electrical Electronics Department Course Digital Systems Design[ELCT 501 Dr Mohamed A Abd El

# sheet9_sol.pdf - Faculty of Information Engineer Technology...

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1 Faculty of Information Engineer & Technology Electrical & Electronics Department Dr. Mohamed A. Abd El Ghany Course: Digital Systems Design [ELCT 501] Eng. Salma Hesham Tutorial # 9 Notes: Critical Path = longest path/ stage in a circuit = minimum allowed clk period Latency = the time delay from a certain input to receive its corresponding output = number of pipeline stages × longest stage Throughput = the maximum allowed clk frequency = 1/longest stage = 1/min period Problem1: Show by a diagram how to efficiently calculate the value R = (a*w) + (b*x) + (c*y) + (d*z) Using the following three system configurations: a) A single-stage pipeline b) A double-stage pipeline c) A triple-stage pipeline For each case: - Show the critical path on the diagram, calculate it, and then calculate the latency and throughput of the system. Assume that the multiplication operation requires 10 time units to take place, while the addition operation requires 4 time units.

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2 a) Single stage pipeline: registers at the output b)
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