537-L7-vm-small-pagetables.pdf - MEMORY SMALLER PAGETABLES Andrea Arpaci-Dusseau CS 537 Fall 2019 ADMINISTRIVIA Project 3 available Shell in Linux(still

537-L7-vm-small-pagetables.pdf - MEMORY SMALLER PAGETABLES...

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MEMORY: SMALLER PAGETABLES Andrea Arpaci-Dusseau CS 537, Fall 2019
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ADMINISTRIVIA - Project 3 available: Shell in Linux (still solo) - Discussion sections (fork() and exec()) - Test scripts available after/during weekend - Midterm 1: Thursday, Oct 10 th from 7:30-9:30pm - Fill out Exam Conflict form in Canvas by TODAY - Two sample exams posted – with answers! - Next discussion sections on practice exam - Canvas Homeworks - “Due” each Tuesday and Thursday
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AGENDA / LEARNING OUTCOMES Memory virtualization How we reduce the size of page tables? What can we do to handle large address spaces?
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RECAP
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When are page tables created? OS creates new page table when creates process OS chooses where process code, heap, and stack are placed in RAM OS sets up page tables to contain initial mappings OS modifies page tables when it allocates more process address space Picks physical locations in RAM code static data Program CPU Memory code static data heap stack Process
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PAGING TRANSLATION STEPS For each mem reference: 1. extract VPN (virt page num) from VA (virt addr) 2. calculate addr of PTE (page table entry) 3. read PTE from memory 4. extract PFN (page frame num) 5. build PA (phys addr) 6. read contents of PA from memory
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Disadvantages of Paging Additional memory reference to page table à Very inefficient Page table must be stored in memory MMU stores only base address of page table Storage for page tables may be substantial Simple page table: Requires PTE for all pages in address space Entry needed even if page not allocated ?
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Strategy: Cache Page Translations CPU RAM memory interconnect PT Translation Cache
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PAGING TRANSLATION STEPS For each mem reference: 1. extract VPN (virt page num) from VA (virt addr) 2. check TLB for VPN if miss: 3. calculate addr of PTE (page table entry) 4. read PTE from memory, replace some entry in TLB 5. extract PFN from TLB (page frame num) 6. build PA (phys addr) 7. read contents of PA from memory
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P1 P2 P2 P1 PT P1 16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB PT P1 pagetable 3 7 9 P2 28 KB TLB Accesses: SEQUENTIAL Example 0 1 2 3 CPU’s TLB PTBR Valid VPN PPN Virt load 0x0000 load 0x0004 load 0x2000 Phys
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HW and OS Roles Who Handles TLB Hit? Who Handles TLB Miss? HW or OS H/W H/W must know where pagetables are stored in memory CR3 register on x86 Pagetable structure fixed and agreed upon between HW and OS HW “walks” known pagetable structure and fills TLB
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HW AND OS ROLES Who Handles TLB MISS? H/W or OS ?
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  • Fall '08
  • ARPACI-DUSSEAU

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