Unformatted text preview: UM10139
LPC214x User manual
Rev. 3 — 4 October 2010 User manual Document information
Info Content Keywords LPC2141, LPC2142, LPC2144, LPC2146, LPC2148, LPC2000, LPC214x,
ARM, ARM7, embedded, 32-bit, microcontroller, USB 2.0, USB device Abstract LPC214x User Manual UM10139 NXP Semiconductors LPC2141/2/4/6/8 Revision history
Rev Date Description 3 20101004 Modifications: •
• New document template applied. •
• IAP call example updated (Section 21.9). •
• RTC usage note updated (Section 18.5 “RTC usage notes”). • PINSEL2 register description updated (Section 6.4.3 “Pin function Select register 2
(PINSEL2 - 0xE002 C014)”). • PWM TCR register bit 3 description updated (Section 16.4.2 “PWM Timer Control
Register (PWMTCR - 0xE001 4004)”). • U0IER register bit description corrected (Section 10.3.6 “UART0 Interrupt Enable
Register (U0IER - 0xE000 C004, when DLAB = 0)”). • U1IER register bit description corrected (Section 11.3.6 “UART1 Interrupt Enable
Register (U1IER - 0xE001 0004, when DLAB = 0)”). • Pin description updated for VBAT, VREF, and RTCX1/2 (Section 5.2 “Pin description for
LPC2141/2/4/6/8”). • SSP CR0 register corrected (Section 13.4.1 “SSP Control Register 0 (SSPCR0 0xE006 8000)”). •
• ADC maximum voltage updated (Table 278 “ADC pin description”). •
• CRP levels updated (Section 21.7 “Code Read Protection (CRP)”). I2C chapter: multiple errors corrected (Chapter 14 “LPC214x I2C-bus interface
WDFEED register description updated Section 16.4.3 “Watchdog Feed register
(WDFEED - 0xE000 0008)”.
CTCR register bit description corrected (Section 18.4.4 “Clock Tick Counter Register
(CTCR - 0xE002 4004)”). Minimum DLL value for use with fractional divider corrected (Section 10.3.4 “UART0
Fractional Divider Register (U0FDR - 0xE000 C028)” and Section 11.3.4 “UART1
Fractional Divider Register (U1FDR - 0xE001 0028)”).
Numerous editorial updates throughout the user manual. 2 20061030 LPC2141/2/4/6/8 user manual 1 20050815 Initial version Contact information
For more information, please visit:
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UM10139 User manual All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 October 2010 © NXP B.V. 2010. All rights reserved. 2 of 354 UM10139
Chapter 1: Introductory information
Rev. 3 — 4 October 2010 User manual 1.1 Introduction
The LPC2141/2/4/6/8 microcontrollers are based on a 32/16 bit ARM7TDMI-S CPU with
real-time emulation and embedded trace support, that combines the microcontroller with
embedded high speed flash memory ranging from 32 kB to 512 kB. A 128-bit wide
memory interface and a unique accelerator architecture enable 32-bit code execution at
the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb
mode reduces code by more than 30 % with minimal performance penalty.
Due to their tiny size and low power consumption, LPC2141/2/4/6/8 are ideal for
applications where miniaturization is a key requirement, such as access control and
point-of-sale. A blend of serial communications interfaces ranging from a USB 2.0 Full
Speed device, multiple UARTs, SPI, SSP to I2Cs, and on-chip SRAM of 8 kB up to 40 kB,
make these devices very well suited for communication gateways and protocol
converters, soft modems, voice recognition and low end imaging, providing both large
buffer size and high processing power. Various 32-bit timers, single or dual 10-bit ADC(s),
10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive
external interrupt pins make these microcontrollers particularly suitable for industrial
control and medical systems. 1.2 Features
• 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
• 8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program memory.
128 bit wide interface/accelerator enables high speed 60 MHz operation. • In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software.
Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms. • EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the
on-chip RealMonitor software and high speed tracing of instruction execution. • USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM.
In addition, the LPC2146/8 provide 8 kB of on-chip RAM accessible to USB by DMA. • One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total of 6/14
analog inputs, with conversion times as low as 2.44 μs per channel. • Single 10-bit D/A converter provides variable analog output.
• Two 32-bit timers/external event counters (with four capture and four compare
channels each), PWM unit (six outputs) and watchdog. • Low power real-time clock with independent power and dedicated 32 kHz clock input.
• Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus
(400 kbit/s), SPI and SSP with buffering and variable data length capabilities. • Vectored interrupt controller with configurable priorities and vector addresses.
• Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.
• Up to nine edge or level sensitive external interrupt pins available.
UM10139 User manual All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 October 2010 © NXP B.V. 2010. All rights reserved. 3 of 354 UM10139 NXP Semiconductors Chapter 1: Introductory information • 60 MHz maximum CPU clock available from programmable on-chip PLL with settling
time of 100 μs. • On-chip integrated oscillator operates with an external crystal in range from 1 MHz to
30 MHz and with an external oscillator up to 50 MHz. • Power saving modes include Idle and Power-down.
• Individual enable/disable of peripheral functions as well as peripheral clock scaling for
additional power optimization. • Processor wake-up from Power-down mode via external interrupt, USB, Brown-Out
Detect (BOD) or Real-Time Clock (RTC). • Single power supply chip with Power-On Reset (POR) and BOD circuits:
– CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O
pads. 1.3 Applications
• Industrial control
Embedded soft modem
General purpose applications 1.4 Device information
Table 1. LPC2141/2/4/6/8 device information Device Number
of pins On-chip
USB RAM On-chip
FLASH Number of
channels Number of
channels Note LPC2141 64 8 kB 2 kB 32 kB 6 - - LPC2142 64 16 kB 2 kB 64 kB 6 1 - LPC2144 64 16 kB 2 kB 128 kB 14 1 UART1 with full
modem interface LPC2146 64 32 kB + 8 kB 2 kB 256 kB 14 1 UART1 with full
modem interface LPC2148 64 32 kB + 8 kB 2 kB 512 kB 14 1 UART1 with full
modem interface  While the USB DMA is the primary user of the additional 8 kB RAM, this RAM is also accessible at any time by the CPU as a general
purpose RAM for data and code storage. 1.5 Architectural overview
The LPC2141/2/4/6/8 consists of an ARM7TDMI-S CPU with emulation support, the
ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced
High-performance Bus (AHB) for interface to the interrupt controller, and the ARM
UM10139 User manual All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 October 2010 © NXP B.V. 2010. All rights reserved. 4 of 354 UM10139 NXP Semiconductors Chapter 1: Introductory information Peripheral Bus (APB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus)
for connection to on-chip peripheral functions. The LPC2141/24/6/8 configures the
ARM7TDMI-S processor in little-endian byte order.
AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the
4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kB address space
within the AHB address space. LPC2141/2/4/6/8 peripheral functions (other than the
interrupt controller) are connected to the APB bus. The AHB to APB bridge interfaces the
APB bus to the AHB bus. APB peripherals are also allocated a 2 megabyte range of
addresses, beginning at the 3.5 gigabyte address point. Each APB peripheral is allocated
a 16 kB address space within the APB address space.
The connection of on-chip peripherals to device pins is controlled by a Pin Connect Block
(see chapter "Pin Connect Block" on page 58). This must be configured by software to fit
specific application requirements for the use of peripheral functions and pins. 1.6 ARM7TDMI-S processor
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets: • The standard 32-bit ARM instruction set.
• A 16-bit THUMB instruction set.
The THUMB set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because THUMB code
operates on the same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that
can be found on official ARM website. UM10139 User manual All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 October 2010 © NXP B.V. 2010. All rights reserved. 5 of 354 UM10139 NXP Semiconductors Chapter 1: Introductory information 1.7 On-chip flash memory system
The LPC2141/2/4/6/8 incorporate a 32 kB, 64 kB, 128 kB, 256 kB, and 512 kB Flash
memory system, respectively. This memory may be used for both code and data storage.
Programming of the Flash memory may be accomplished in several ways: over the serial
built-in JTAG interface, using In System Programming (ISP) and UART0, or by means of
In Application Programming (IAP) capabilities. The application program, using the IAP
functions, may also erase and/or program the Flash while the application is running,
allowing a great degree of flexibility for data storage field firmware upgrades, etc. When
the LPC2141/2/4/6/8 on-chip bootloader is used, 32 kB, 64 kB, 128 kB, 256 kB, and
500 kB of Flash memory is available for user code.
The LPC2141/2/4/6/8 Flash memory provides minimum of 100,000 erase/write cycles and
20 years of data-retention. 1.8 On-chip Static RAM (SRAM)
On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip
SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2141/2/4/6/8 provide
8/16/32 kB of static RAM, respectively.
The LPC2141/2/4/6/8 SRAM is designed to be accessed as a byte-addressed memory.
Word and halfword accesses to the memory ignore the alignment of the address and
access the naturally-aligned value that is addressed (so a memory access ignores
address bits 0 and 1 for word accesses, and ignores bit 0 for halfword accesses).
Therefore valid reads and writes require data accessed as halfwords to originate from
addresses with address line 0 being 0 (addresses ending with 0, 2, 4, 6, 8, A, C, and E in
hexadecimal notation) and data accessed as words to originate from addresses with
address lines 0 and 1 being 0 (addresses ending with 0, 4, 8, and C in hexadecimal
notation). This rule applies to both off and on-chip memory usage.
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls
during back-to-back writes. The write-back buffer always holds the last data sent by
software to the SRAM. This data is only written to the SRAM when another write is
requested by software (the data is only written to the SRAM when software does another
write). If a chip reset occurs, actual SRAM contents will not reflect the most recent write
request (i.e. after a "warm" chip reset, the SRAM does not reflect the last write operation).
Any software that checks SRAM contents after reset must take this into account. Two
identical writes to a location guarantee that the data will be present after a Reset.
Alternatively, a dummy write operation before entering idle or power-down mode will
similarly guarantee that the last data written will be present in SRAM after a subsequent
Reset. UM10139 User manual All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 October 2010 © NXP B.V. 2010. All rights reserved. 6 of 354 UM10139 NXP Semiconductors Chapter 1: Introductory information 1.9 Block diagram
TDI(1) TCK(1) TEST/DEBUG
INTERFACE LPC2141/42/44/46/48 ARM7TDMI-S
P1[31:16] FAST GENERAL
PURPOSE I/O trace XTAL2
XTAL1 TDO(1) signals AHB BRIDGE PLL0 EMULATION
TRACE MODULE TMS(1)
clock AMBA AHB
(Advanced High-performance Bus) ARM7 local bus
CONTROLLER 8/16/32 kB
FLASH 8 kB RAM
AHB TO APB
BRIDGE 8 × CAP
8 × MAT
AD0[4:0] AOUT(4) EXTERNAL
INTERRUPTS USB 2.0 FULL-SPEED
WITH DMA(3) CAPTURE/
TIMER 0/TIMER 1 I2C SERIAL
INTERFACES 0 AND 1 A/D CONVERTERS
0 AND 1(2) AD1[7:0](2) AHB
DIVIDER APB (ARM
SSEL0,1 SPI AND SSP
SERIAL INTERFACES D/A CONVERTER(4) TXD0,1
DCD1(2), RI1(2) UART0/UART1
PURPOSE I/O PWM[6:1] RTCX1
REAL TIME CLOCK PWM0 RTCX2
CONTROL 002aab560 (1) Pins shared with GPIO.
(2) LPCC2144/6/8 only.
(3) USB DMA controller with 8 kB of RAM accessible as general purpose RAM and/or DMA is available in LPC2146/8 only.
(4) LPC2142/4/6/8 only. Fig 1. LPC2141/2/4/6/8 block diagram
UM10139 User manual All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 October 2010 © NXP B.V. 2010. All rights reserved. 7 of 354 UM10139
Chapter 2: LPC214x Memory mapping
Rev. 3 — 4 October 2010 User manual 2.1 Memory maps
The LPC2141/2/4/6/8 incorporates several distinct memory regions, shown in the
following figures. Figure 2 shows the overall map of the entire address space from the
user program viewpoint following reset. The interrupt vector area supports address
remapping, which is described later in this section.
4.0 GB 0xFFFF FFFF
0xF000 0000 3.75 GB
APB PERIPHERALS 0xE000 0000 3.5 GB
3.0 GB RESERVED ADDRESS SPACE 0xC000 0000
0x8000 0000 2.0 GB
(12 kB REMAPPED FROM ON-CHIP FLASH MEMORY) 0x7FFF D000
0x7FFF CFFF RESERVED ADDRESS SPACE
8 kB ON-CHIP USB DMA RAM (LPC2146/2148)
RESERVED ADDRESS SPACE
32 kB ON-CHIP STATIC RAM (LPC2146/2148) 0x4000 8000
0x4000 3FFF 16 kB ON-CHIP STATIC RAM (LPC2142/2144)
8 kB ON-CHIP STATIC RAM (LPC2141)
1.0 GB 0x4000 0000
0x3FFF FFFF RESERVED ADDRESS SPACE
TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY (LPC2148)
TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY (LPC2146)
TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY (LPC2144)
TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY (LPC2142)
TOTAL OF 32 kB ON-CHIP NON-VOLATILE MEMORY (LPC2141)
0x0000 0000 0.0 GB Fig 2.
UM10139 User manual System memory map
All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 October 2010 © NXP B.V. 2010. All rights reserved. 8 of 354 UM10139 NXP Semiconductors Chapter 2: LPC214x Memory mapping 4.0 GB 0xFFFF FFFF
0xFFDF FFFF 4.0 GB - 2 MB RESERVED 0xF000 0000
0xEFFF FFFF 3.75 GB RESERVED 0xE020 0000
0xE01F FFFF 3.5 GB + 2 MB
APB PERIPHERALS 0xE000 0000 3.5 GB Fig 3. Peripheral memory map Figures 3 through 4 and Table 2 show different views of the peripheral address space.
Both the AHB and APB peripheral areas are 2 megabyte spaces which are divided up into
128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the
address decoding for each peripheral. All peripheral register addresses are word aligned
(to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane
mapping hardware that would be required to allow byte (8-bit) or half-word (16-bit)
UM10139 User manual All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 October 2010 © NXP B.V. 2010. All rights reserved. 9 of 354 UM10139 NXP Semiconductors Chapter 2: LPC214x Memory mapping accesses to occur at smaller boundaries. An implication of this is that word and half-word
registers must be accessed all at once. For example, it is not possible to read or write the
upper byte of a word register separately. VECTORED INTERRUPT CONTROLLER 0xFFFF F000 (4G - 4K) 0xFFFF C000 (AHB PERIPHERAL #126)
0xFFFF 8000 (AHB PERIPHERAL #125)
0xFFFF 4000 (AHB PERIPHERAL #124)
0xFFFF 0000 0xFFE1 0000 (AHB PERIPHERAL #3)
0xFFE0 C000 (AHB PERIPHERAL #2)
0xFFE0 8000 (AHB PERIPHERAL #1)
0xFFE0 4000 (AHB PERIPHERAL #0)
0xFFE0 0000 AHB section is 128 x 16 kB blocks (totaling 2 MB).
APB section is 128 x 16 kB blocks (totaling 2MB). Fig 4. UM10139 User manual AHB peripheral map All information provided in this document is subject to legal disclaimers. Rev. 3 — 4 October 2010 © NXP B.V. 2010. All rights reserved. 10 of 354 UM10139 NXP Semiconductors Chapter 2: LPC214x Memory mapping Table 2. APB peripherals and base addresses APB peripheral Base address Peripheral name 0 0xE000 0000 Watchdog timer 1 0xE000 4000 Timer 0 2 0xE000 8000 Timer 1 3 0xE000 C000 UART0 4 0xE001 0000 UART1 5 0xE001 4000 PWM 6 0xE001 8000 Not used 7 0xE001 C000 I2C0 8 0xE002 0000 SPI0 9 0xE002 4000 RTC 10 0xE002 8000 GPIO 11 0xE002 C000 Pin connect block 12 0xE003 0000 Not used 13 0xE003 4000 ADC0 14 - 22 0xE003 8000
0xE005 8000 Not used 23 0xE005 C000 I2C1 24 0xE006 0000 ADC1 25 0xE006 4000 Not used 26 0xE006 8000 SSP 27 0xE006 C000 DAC 28 - 35 0xE007 0000
0xE008 C000 Not used 36 0xE009 0000 USB 37 - 126 0xE009 4000
0xE01F 8000 Not used 127 0xE01F C000 System Control Block 2.2 LPC2141/2142/2144/2146/2148 memory re-mapping and boot block
2.2.1 Memory map concepts and operating modes
The basic concept on the LPC2141/2/4/6/8 is that each memory area has a "natural"
location in the memory map. This is the address range for which code residing in that area
is written. The bulk of each memory space remains permanently fixed in the same
location, eliminating the need to have portions of the code designed to run in different
Because of the location of the interrupt vectors on the ARM7 processor (at addresses
0x0000 0000 through 0x0000 001C, as shown in Table 3 below), a small portion of the
Boot Block and SRAM spaces need to be re-mapped in order to allow alternative uses of
interrupts in the different operating modes described in Table 4. Re-mapping of the
interrupts is accomplished via the Memory Mapping...
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