FALLSEM2015-16_CP0619_13-Oct-2015_RM01_binaryupdowncounter.docx - Date D DESIGN AND VERIFICATION OF 4 BIT BINARY UP/DOWN COUNTER WITH LOAD ENABLE Ex No

# FALLSEM2015-16_CP0619_13-Oct-2015_RM01_binaryupdowncounter.docx

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Date : 20/10/15 Ex No : 10 D DESIGN AND VERIFICATION OF 4 BIT BINARY UP/DOWN COUNTER WITH LOAD ENABLE AIM To verify the operation of 4bit binary up/down counter using verilog. APPARATUS REQUIRED Xilinx ISE 12.1 Software. THEORY: The sequence of states may follow the binary number sequence or other sequence of states. A counter that follow the binary number sequence is called a binary counter. A n- bit binary counter consist of n flip flop and can count in binary from 0 through 2 n -1. Counter are available in two categories: ripple counter and synchronous counter. In ripple counter, a flip-flop output transition serves as a source for triggering other flip-flop In other word ,the C input of some or all flip-flop are triggered, not by the common clock pluses ,but rather by the transition that occurs in other flip-flop output. In synchronous counter, the C in- put of all flip-flop rceive the common clock. CIRCUIT DIAGRAM: Binary up Counters A synchronous binary counter counts from 0 to 2 N

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