exam 1p pg11.jpeg - 5:47 PM Sun Oct 6 94 a mil.ufl.edu University of Florida EEL 3701-Spring 2019 Dr Eric M Schwartz Department of Electrical Computer

# exam 1p pg11.jpeg - 5:47 PM Sun Oct 6 94 a mil.ufl.edu...

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Unformatted text preview: 5:47 PM Sun Oct 6 94% a mil.ufl.edu University of Florida EEL 3701-Spring 2019 Dr. Eric. M. Schwartz Department of Electrical & Computer Engineering Wednesday, 27 February 2019 Page 8/1 1 Exam 1P Last Name, First Name [17%] 8. Design a system that "counts" as shown. The system must 3 min asynchronously go to state "2" when Restart (active-high) goes true. W is an active-low signal that determines the next "count" after "0," as Restart shown in the figure. Use a T-FF for the most significant bit of your design, W = L. a JK-FF for the least significant bit, and D-FF(s) for any other bits you might need. An active-low output, Y should be true when the "count" is 5 "5." All other outputs should be active-high. Note: All the given FFs have W=0 asynchronous clear and set inputs as shown. (2%) a) Draw a functional block diagram (showing all the inputs, all the outputs, 4 min and the functional blocks). Put your design in the dashed box with the inputs and outputs going into or out of the box, on the left or right, respectively. This is not a circuit diagram. Outputs comb logic y ( L ) W ( 4) - logic X2 ( H ) SET Resta(tl ) XI (H ) Xo (A ) SET Q (7%) b) Complete the next-state truth table (in counting order). 6 min W a. J X - XOX X- Ko O O - C Qutisk O DO OX C I X D-COC-3- - X X X - x Cob -coolx 10 1 1 XO...
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