lec14-handouts-rev1.pdf - ODT CS RAS CAS WE Command decode Control logic CKE CK CK CS 150 Digital Design Mode registers 16 Refresh 14 counter 14 Row 14

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Unformatted text preview: ODT CS# RAS# CAS# WE# Command decode Control logic CKE CK CK# CS 150 Digital Design Mode registers 16 Refresh 14 counter 14 Row- 14 address MUX Bank 3 Bank 2 Bank 1 Bank 0 rowaddress 16,384 latch and decoder Lecture 14 – DRAM Bank 3 Bank 2 Bank 1 Bank 0 COL0, COL1 32 Memory array (16,384 x 256 x 32) Read latch 8 8 8 MUX 8 DQS generator Sense amplifiers 8,192 2 A0–A13, BA0, BA1 Address 16 register I/O gating DM mask logic Bank control logic 2011-10-13 2 Elad Alon 256 (x32) Columnaddress counter/ latch 10 Column decoder 8 2 8 Data D Input registers 1 1 1 1 32 4 Write FIFO Mask 1 and 1 32 drivers 8 internal CK out 32 8 CK, CK# CK in Data 8 8 8 8 today’s lecture by John Lazzaro 1 1 8 8 COL0, COL1 TAs: Daiwei Li, James Parker, Dan Yeager Figure 5: 32 Meg x 16 Functional Block Diagram www-inst.eecs.berkeley.edu/~cs150/ CS 150 L14: DRAM UC Regents Fall 2011 © UCB 1 ODT CKE CK CK# Control Logic CS# RAS# CAS# WE# Command decode Today’s Lecture: DRAM Mode registers Refresh 13 counter Row- 13 address MUX DRAM, Xilinx, and You 15 13 Bank 3 Bank 2 Bank 1 Bank 0 rowAddress 8,192 latch and decoder COL0, COL1 Bank 3 Bank 2 Bank 1 Bank 0 64 Read latch Memory array (8,192 x 256 x 64) Sense amplifiers 16 16 16 MUX 16 DQS generat Inpu regist 2 16,384 64 2 A0–A12, BA0, BA1 15 Address register DRAM: Bottom-up 10 DRAM: Top-down PDF: 09005aef82f1e6e2 512MbDDR2.pdf - Rev. O 7/09 EN CS 150 L14: DRAM 2 Columnaddress counter/ latch 2 I/O gating DM mask logic Bank control logic 8 Write FIFO Mask 64 and drivers 256 (x64) 8 Column decoder D Internal CK, CK# 2 CK out CK in 64 Data 2 2 16 16 16 16 COL0, COL1 12 Micron Technology UC Regents Fall 2011 © UCB 2 2 14 WP A0 A1 A2 Module height: 30mm (1.18in) -80E -800 -667 -53E Y None I Marking Figure 1: 200-Pin SODIMM (MO-224 R/C C) Options 3 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DDR2 SDRAM ! Operating temperature " Commercial (0°C # TA # +70°C) " Industrial (–40°C # TA # +85°C)1 ! Package " 200-pin DIMM (lead-free) ! Frequency/CL2 " 2.5ns @ CL = 5 (DDR2-800) " 2.5ns @ CL = 6 (DDR2-800) " 3.0ns @ CL = 5 (DDR2-667) " 3.75ns @ CL = 4 (DDR2-533)3 DQS7 DQS7# DM7 R DDR2 SO-DIMM Module Figure 2: Functional Block Diagram 128MB, 256MB, 512MB (x64, SR) 200-Pin DDR2 SODIMM Features Functional Block Diagram DDR2 SDRAM SODIMM Dual Inline Memory Module MT4HTF1664HY – 128MB MT4HTF3264HY – 256MB MT4HTF6464HY – 512MB Features ! ! ! ! ! ! ! U2 UC Regents Fall 2011 © UCB CS 150 L14: DRAM U4 DRAM chips are wired in parallel and run in lockstep. DQS3 DQS3# DM3 SA0 SA1 VSS VSS SDA U5 Serial PD SCL DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DDR2 SDRAM VSS U1 CS# CK0 CK0# DDR SDRAM U1, U2 CK1 CK1# DDR SDRAM U3, U4 DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ DDR2 SDRAM VREF DQS5 DQS5# DM5 DQS1 DQS1# DM1 DQS6 DQS6# DM6 Serial PD VDDSPD DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ CS# VDD U3 CAS#: DDR2 SDRAM WE#: DDR2 SDRAM CKE0: DDR2 SDRAM ODT0: DDR2 SDRAM CAS# WE# CKE0 ODT0 DQS4 DQS4# DM4 DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 BA[2/1:0]: DDR2 SDRAM A[12:0]: DDR2 SDRAM RAS#: DDR2 SDRAM BA[2/1:0] A[12:0] RAS# CS# CS# DQS0 DQS0# DM0 DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ DQS DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ DQS2 DQS2# DM2 3 S0# UC Regents Fall 2011 © UCB 128MB, 256MB, 512MB (x64, SR) 200-Pin DDR2 SODIMM Functional Block Diagram 3 CS 150 L14: DRAM 33 23 43 17 SO-DIMM: Small-Outline, ! 200-pin, small-outline dual in-line memory module (SODIMM) ! Fast data transfer rates: PC2-3200, PC2-4200, PC2-5300, or PC2-6400 ! 128MB (16 Meg x 64), 256MB (32 Meg x 64), or 512MB (64 Meg x 64) ! VDD = VDDQ = 1.8V ! VDDSPD = 1.7–3.6V ! JEDEC-standard 1.8V I/O (SSTL_18-compatible) UG347_02_112906 ! Differential data strobe (DQS, DQS#) option ! 4n-bit prefetch architecture Figure 1-3: Detailed Description of Virtex-5 ML505 Components! (Back) Multiple internal device banks for concurrent operation Note: The label on the CompactFlash (CF) card shipped with your board might differProgrammable from the one CAS latency (CL) shown. Posted CAS additive latency (AL) WRITE latency = READ latency - 1 tCK Programmable burst lengths (BL): 4 or 8 Adjustable data-output drive strength 64ms, 8192-cycle refresh On-die termination (ODT) DDR2: Double-Data Rate, 2nd generation hapter 1: ML505/ML506/ML507 Evaluation Platform DDR2 SO-DIMM on ML505 Board 4 The infrastructure module generates the FPGA clock and reset signals. When differential clocking is used, sys_clk_p, sys_clk_n, clk_200_p, and clk_200_n signals appear. When single-ended clocking is used, sys_clk and idly_clk_200 signals appear. In addition, clocks are available for design use and a 200 MHz clock is provided for the IDELAYCTRL primitive. Differential and single-ended clocks are passed through global clock buffers before connecting to a DCM. For differential clocking, the output of the sys_clk_p/sys_clk_n buffer is single-ended and is provided to the DCM input. Likewise, for single-ended clocking, sys_clk is passed through a buffer and its output is provided to the DCM input. The outputs of the DCM are clk_0 (0° phase-shifted version of the input clock) and clk_90 (90° phase-shifted version of the input clock). After the DCM is locked, the design is in the reset state for at least 25 clocks. The infrastructure module also generates all of the reset signals required for the design. Project controller: Xilinx-supplied IP Your project’s Verilog code sees a FIFO R/W interface. Xilinx IP translates FIFO requests to DRAM commands. DDR2 SODIMM Figure 3-7 is a detailed block diagram of the DDR2 SDRAM controller. The five blocks shown are the subblocks of the top module. User backend signals are provided by the tool for designs with a testbench. The user has to drive these signals for designs without a testbench. The functions of these blocks are explained in the subsections following the figure. I User Interface User Backend app_af_addr Backend FIFOs Read/Write Address FIFO app_wdf_data DDR2 SDRAM Controller ctrl_rden ctrl_waf_rden ctrl_dqs_rst ctrl_dqs_en ctrl_wren ctrl_wdf_rden app_mask_data ctrl_dummyread_start app_wdf_wren wdf_almost_full Write Data FIFOs af_almost_full Read Data Compare Module address/controls af_empty app_af_wren Address and Data Generation ck/ck_n af_addr read_data_fifo_out read_data_valid DDR2 SDRAM wdf_data Physical Layer read_data_rise/fall Read Data FIFOs phy_dly_slct_done dq dqs rd_en_delayed_rise/fall burst_length_div2 init_done clk_tb reset_tb Virtex-4 FPGA UG086_c3_07_091508 Figure 3-7: CS 150 L14: DRAM DDR2 Memory Controller Block Diagram UC Regents Fall 2011 © UCB Controller The DDR2 SDRAM ddr2_controller accepts and decodes user commands and generates read, write, and refresh commands. The DDR2 SDRAM controller also generates signals for other modules. The memory is initialized and powered-up using a defined process. The controller state machine handles the initialization process upon power-up. After memory initialization, the controller issues dummy read commands. During dummy reads, the 5 Today’s Lecture: DRAM Memory Interface Solutions User Guide UG086 (v3.6) September 21, 2010 137 DRAM, Xilinx, and You To understand the DRAM: Bottom-up DRAM controller, you need to understand how a DRAM chip DRAM: Top-down works. Otherwise, it just seems like magic. CS 150 L14: DRAM UC Regents Fall 2011 © UCB 6 Capacitance CS 150 L14: DRAM UC Regents Fall 2011 © UCB 7 Recall: Building a capacitor Top Plate Dielectric Bottom Plate CS 150 L14: DRAM Conducts electricity well. (metal, doped polysilicon) An insulator. Does not conducts electricity at all. (air, glass (silicon dioxide)) Conducts electricity well (metal, doped polysilicon) UC Regents Fall 2011 © UCB 8 Recall: Capacitors in action Because the dielectric is an insulator, and does not conduct. +++ +++ I=0 --- --- After circuit “settles” ... Q = C V = C * 1.5 Volts (D cell) Q: Charge stored on capacitor C: The capacitance of the device: function of device shape and type of dielectric. 1.5V +++ +++ After battery is removed: Still, Q = C * 1.5 Volts Capacitor “remembers” charge CS 150 L14: DRAM --- --UC Regents Fall 2011 © UCB 9 Storing computational state as charge State is coded as the amount of energy stored by a device. +++ +++ --- --- 1.5V +++ +++ --- --- State is read by sensing the amount of energy Problems: noise changes Q (up or down), parasitics leak or source Q. Fortunately, Q cannot change instantaneously, but that only gets us in the ballpark. CS 150 L14: DRAM UC Regents Fall 2011 © UCB 10 MOS Transistors Two diodes and a capacitor in an interesting arrangement. So, we begin with a diode review ... CS 150 L14: DRAM UC Regents Fall 2011 © UCB 11 Diodes in action ... Resistor Light emitting diode (LED) Light on? Yes! Light on? No! CS 150 L14: DRAM UC Regents Fall 2011 © UCB 12 Diodes: Current vs Voltage Diode is off I ≈ - Io Anode + I Diode is on I ≈ Io exp(V/Vo) V Cathode I = Io [exp(V/Vo) - 1] Vo range: 25mV to 60 mV Io range: 1fA to 1nA CS 150 L14: DRAM UC Regents Fall 2011 © UCB 13 How to make a silicon diode ... Wafer cross-section Cathode: - - n+ V p- Anode: + + p- region depletion region depletion region Wafer doped p-type At V ≈ 0, “hill” too high for electrons to diffuse up. e l e n+ region c t r o n For holes, going “downhill” is hard. CS 150 L14: DRAM no carriers V controls hill. e n e r g y UC Regents Fall 2011 © UCB 14 Note: IC Diodes are biased “off”! V1 V2 V1 V2 n+ n+ p0 V - “ground” V1, V2 > 0V. Diodes “off”, only current is Io “leakage”. I = Io [exp(V/Vo) - 1] Anodes of all diodes on wafer connected to ground. CS 150 L14: DRAM UC Regents Fall 2011 © UCB 15 MOS Transistors Two diodes and a capacitor in an interesting arrangement ... CS 150 L14: DRAM UC Regents Fall 2011 © UCB 16 What we want: the perfect switch. V1 Switch is off. V1 is not connected to V2. n+ V2 n+ p- V1 Switch is on. V1 is connected to V2. V2 n+ We want to turn a p-type region into an n-type region under voltage control. We need electrons to fill valence holes and add conduction band electrons +++ +++ p- --- --- CS 150 L14: DRAM UC Regents Fall 2011 © UCB 17 An n-channel MOS transistor (nFET) Vg = 0V Vd = 1V I ≈ nA n+ dielectric Vs = 0V n+ p- Vg = 1V Vd = 1V +++++++++ I ≈ μA dielectric ------------------n+ p- Polysilicon gate, dielectric, and substrate form a capacitor. nFet is off (I is “leakage”) Vs = 0V n+ Vg = 1V, small region near the surface turns from p-type to n-type. nFet is on CS 150 L14: DRAM UC Regents Fall 2011 © UCB 18 Mask set for an n-Fet (circa 1986) Vg = 0V Vd = 1V I ≈ nA n+ dielectric p- Top-down view: CS 150 L14: DRAM Vs = 0V n+ Masks #1: n+ diffusion #2: poly (gate) #3: diff contact #4: metal Layers to do p-Fet not shown. Modern processes have 6 to 10 metal layers (or more) (in 1986: 2). UC Regents Fall 2011 © UCB 19 Dynamic Memory Cells CS 150 L14: DRAM UC Regents Fall 2011 © UCB 20 Recall: Capacitors in action Because the dielectric is an insulator, and does not conduct. After circuit “settles” ... +++ +++ I=0 --- --- Q = C V = C * 1.5 Volts (D cell) Q: Charge stored on capacitor C: The capacitance of the device: function of device shape and type of dielectric. 1.5V +++ +++ After battery is removed: Still, Q = C * 1.5 Volts Capacitor “remembers” charge --- --- CS 150 L14: DRAM UC Regents Fall 2011 © UCB 21 DRAM cell: 1 transistor, 1 capacitor Vdd “Bit Line” “Word Line” Word Line Vdd Capacitor “Bit Line” “Bit Line” n+ oxide n+ oxide ------ pWord Line and Vdd run on “z-axis” CS 150 L14: DRAM Why Vcap values start out at ground. Vdd Vcap Diode leakage current. UC Regents Fall 2011 © UCB 22 A 4 x 4 DRAM array (16 bits) .... CS 150 L14: DRAM UC Regents Fall 2011 © UCB 23 Invented after SRAM, by Robert Dennard CS 150 L14: DRAM UC Regents Fall 2011 © UCB 24 DRAM Circuit Challenge #1: Writing Vdd Vdd Vgs Vdd Vc Vdd - Vth. Bad, we store less charge. Why do we not get Vdd? Ids = k [Vgs -Vth]^2 , but “turns off” when Vgs <= Vth! Vgs = Vdd - Vc. When Vdd - Vc == Vth, charging effectively stops! CS 150 L14: DRAM UC Regents Fall 2011 © UCB 25 DRAM Challenge #2: Destructive Reads Bit Line +++++++ (stored charge from cell) (initialized to a low voltage) Word Line + + + + s + Vg + + 0 -> Vdd Vc -> 0 Vdd Raising the word line removes the charge from every cell it connects to! DRAMs write back after each read. CS 150 L14: DRAM UC Regents Fall 2011 © UCB 26 DRAM Circuit Challenge #3a: Sensing Assume Ccell = 1 fF Bit line may have 2000 nFet drains, assume bit line C of 100 fF, or 100*Ccell. Ccell holds Q = Ccell*(Vdd-Vth) 100*Ccell Ccell When we dump this charge onto the bit line, what voltage do we see? dV = [Ccell*(Vdd-Vth)] / [100*Ccell] dV = (Vdd-Vth) / 100 ≈ tens of millivolts! In practice, scale array to get a 60mV signal. CS 150 L14: DRAM UC Regents Fall 2011 © UCB 27 DRAM Circuit Challenge #3b: Sensing ... How do we reliably sense a 60mV signal? Compare the bit line against the voltage on a “dummy” bit line. “sense amp” Bit line to sense + ? “Dummy” bit line. Dummy bit line Cells hold no charge. CS 150 L14: DRAM UC Regents Fall 2011 © UCB 28 DRAM Challenge #4: Leakage ... Bit Line Word Line + + + + + + + Vdd Parasitic currents leak away charge. Solution: “Refresh”, by rewriting cells at regular intervals (tens of milliseconds) n+ oxide n+ oxide ------ p- Diode leakage ... CS 150 L14: DRAM UC Regents Fall 2011 © UCB 29 DRAM Challenge #5: Cosmic Rays ... Bit Line Word Line + + + + + + + Vdd Cell capacitor holds 25,000 electrons (or less). Cosmic rays that constantly bombard us can release the charge! Solution: Store extra bits to detect and correct random bit flips (ECC). n+ oxide pCS 150 L14: DRAM n+ oxide ------ Cosmic ray hit. UC Regents Fall 2011 © UCB 30 DRAM Challenge 6: Yield If one bit is bad, do we throw chip away? ... Extra bit lines. Used for “sparing”. Solution: add extra bit lines (i.e. 80 when you only need 64). During testing, find the bad bit lines, and use high current to burn away “fuses” put on chip to remove them. CS 150 L14: DRAM UC Regents Fall 2011 © UCB 31 Moore’s Law for’CPUs DRAMs Moore s Lawand - 2005 Transistors Per Die 1010 109 108 107 106 105 104 1K 103 102 1G 2G 512M 256M 128M Itanium™ 2 Processor 64M Itanium™ Processor 16M ® 4 Processor Pentium 4M ® Pentium III Processor 1M ® II Processor Pentium 256K ® Pentium Processor 64K 486™ 486™ Processor 16K 386™ 386™ Processor 4K 80286 8080 8086 8008 1965 Data (Moore) 4004 Memory 101 Microprocessor 100 1960 1965 1970 1975 1980 1985 1990 1995 2000 2005 2010 From: “Facing the Hot Chips Challenge Again”, Bill Holt, Intel, presented at Hot Chips 17, 2005. Source: Intel CS 150 L14: DRAM 4 UC Regents Fall 2011 © UCB 32 Main driver: device scaling ... Cost Driver Scaling: The Fundamental 350nm 200mm 250nm 200mm Twice the circuitry in the same space (architectural innovation) 180nm 200mm 130nm 200mm The same circuitry in half the space (cost reduction) OR 90nm 300mm = 65nm 300mm Dual Core Half the die size for the same capability than in the prior process From: “Facing the Hot Chips Challenge Again”, Bill Holt, Intel, presented at Hot Chips 17, 2005. CS 150 L14: DRAM UC Regents Fall 2011 © UCB 6 33 Scaling: Fundamental Driver ProcessThe Scaling: WhyCost chips don’t fry IC process scaling (“Moore’s Law”) Process Advances Still Scale Power 350nm 200mm 250nm 200mm CV2 Scaling Twice the circuitry in the same space (architectural innovation) 180nm 200mm OR 130nm 200mm The same circuitry in half the space (cost reduction) = 90nm 300mm 65nm 300mm Dual Core Half the die size for the same capability than in the prior process 32nm 45nm 65nm 90nm .13!m .18!m .25!m .35!m 6 Due to reducing V and C (length and width of Cs decrease, but plate distance gets smaller). Recent slope more shallow because V is being scaled less aggressively. From: “Facing the Hot Chips Challenge Again”, Bill Holt, Intel, presented at Hot Chips 17, 2005. but the rate has slowed and collaboration is required CS 150 L14: DRAM UC Regents Fall 2011 © UCB 16 34 DRAM Challenge 7: Scaling Each generation of IC technology, we shrink width and length of cell. If Ccell and drain capacitances scale together, number of bits per bit line stays constant. dV ≈ 60 mV= [Ccell*(Vdd-Vth)] / [100*Ccell] Problem 1: Number of arrays per chip grows! Problem 2: Vdd may need to scale down too! Solution: Constant Innovation of Cell Capacitors! CS 150 L14: DRAM UC Regents Fall 2011 © UCB 35 Poly-diffusion Ccell is ancient history Vdd “Bit Line” “Word Line” Word Line Vdd Capacitor “Bit Line” “Bit Line” n+ oxide n+ oxide ------ pWord Line and Vdd run on “z-axis” CS 150 L14: DRAM UC Regents Fall 2011 © UCB 36 Early replacement: “Trench” capacitors CS 150 L14: DRAM UC Regents Fall 2011 © UCB 37 Final generation of trench capacitors The companies that kept scaling trench capacitors for commodity DRAM chips went out of business. CS 150 L14: DRAM UC Regents Fall 2011 © UCB 38 Modern cells: “stacked” capacitors CS 150 L14: DRAM UC Regents Fall 2011 © UCB 39 SONG et al.: A 31 ns RANDOM CYCLE VCAT-BASED 4F DRAM In the labs: Vertical cell transistors ... 880 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010 A 31 ns Random Cycle VCAT-Based 4F DRAM Fig. 1. (a) The section of surrounding-gate vertical channel access tranWithcross Manufacturability and Enhanced Cell Efficiency sistor (VCAT).Ki-Whan (b)Song, The schematic diagram of Kim, VCAT-based 4FKim, DRAM cell Jin-Young Kim, Jae-Man Yoon, Sua Kim, Huijung Hyun-Woo Chung, Hyungi Kanguk Kim, Hwan-Wook Park, Hyun Chul Kang, Nam-Kyun Tak, Dukha Park, Woo-Seop Kim, Member, IEEE, array. Yeong-Taek Lee, Yong Chul Oh, Gyo-Young Jin, Jeihwan Yoo, Donggun Park, Senior Member, IEEE, Kyungseok Oh, Changhyun Kim, Senior Member, IEEE, and Young-Hyun Jun CS 150 L14: DRAM UC Regents Fall 2011 © UCB 40 Abstract—A functional 4F DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance VCAT has been developed showing excellent Ion-Ioff characteristics with more than twice turn-on current compared Thus, the innovative cell size reduction technology which does not necessarily accompany scale-down in ‘F’ gains weight again these days. Although 6F has been believed to be the approximate limit of memory cells without going to MLC tech- Fig. 2. – technology. Figure 4: 64 Meg x 8 Functional Block Diagram Micron 50nm 1-Gbit DDR2 die photo ODT CS# RAS# CAS# WE# Control logic Command decode CKE CK CK# Mode registers 16 Refresh 14 counter 14 Row- 14 address MUX Bank 3 Bank 2 Bank 1 Bank 0 rowaddress 16,384 latch and decoder Bank 3 Bank 2 Bank 1 Bank 0 32 Memory array (16,384 x 256 x 32) Read latch 8 8 8 D MUX 8 8,192 A0–A13, BA0, BA1 Address 16 register I/O gating DM mask logic Bank control logic 2 256 (x32) Columnaddress counter/ latch 10 Column decoder 8 2 8 DRV Data DQS generator Sense amplifiers 2 CK, COL0, COL1 2 DQS, DQ Input registers 1 1 1 1 32 4 Write FIFO Mask 1 and 1 32 drivers 8 internal CK out 32 8 CK, CK# CK in Data 8 8 8 8 1 1 1 R 8 8 8 COL0, COL1 2 CS 150 L14: DRAM UC Regents Fall 2011 © UCB 41 Figure 5: 32 Meg x 16 Functional Block Diagram Today’s Lecture: DRAM ODT CKE CK CK# Control Logic CS# RAS# CAS# WE# Command decode DRAM, Xilinx, and You Mode registers Refresh 13 counter Row- 13 address MUX DRAM: Bottom-up 15 13 Bank 3 Bank 2 Bank 1 Bank 0 rowAddress 8,192 latch and decoder 64 Read latch Memory array (8,192 x 256 x 64) Sense amplifiers 16 16 16 MUX 16 A0–A12, BA0, BA1 15 Address register DRAM: Top-down 10 2 Columnaddress counter/ latch 8 Write FIFO Mask 64 and drivers 256 (x64) 8 Column decoder Internal CK, CK# CK out CK in 2 COL0, COL1 CS 150 L14: DRAM 4 UDQ LDQ Input registers 2 2 64 I/O gating DM mask logic Bank control logic 16 Data DQS generator 16,384 2 C COL0, COL1 Ban...
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