1 Fall 2011 EECS150 Lecture 9 Page 1 EECS150 - Digital Design Lecture 9 – Project Introduction (I), Serial I/O September 22, 2011 Elad Alon Electrical Engineering and Computer Sciences University of California, Berkeley Fall 2011 EECS150 Lecture 9 Page 2 Announcements • Homework #3 due today • Homework #4 out tonight – Due next Thurs.
2 Fall 2011 EECS150 Lecture 9 Page 3 Project Overview A. MIPS150 pipeline structure B. Serial Interface C. Memories, project memories and FPGAs D. Video subsystem E. Project specification and grading standard Fall 2011 EECS150 Lecture 9 Page 4 MIPS 5-stage Pipeline Review (IF) Use PC register as address to instruction memory (IMEM) and retrieve next instruction. (ID) Generate control signals, retrieve register values from regfile. (EX) Use ALU to compute result, memory address, or compare registers. (DM) Read or write data memory (DMEM). (WB) Send result back to regfile.
3 Fall 2011 EECS150 Lecture 9 Page 5 Control Hazard Example MIPS 5-stage Pipeline beq $1, $2, L1 IF ID EX DM WB add $5, $3, $4 IF ID EX DM WB L1: sub $5, $3, $4 IF ID EX DM WB branch address ready here but needed here! Register values are known here, move branch compare and target address generation to here. Note: Still one remaining cycle of branch delay. “Architected branch delay slot” on MIPS allows compiler to deal with the delay. Other processors without architected branch-delay slot use branch predictors or pipeline stalling. cycle Fall 2011 EECS150 Lecture 9 Page 6 Modify the Datapath to Support Early Branch