lec19_cp4.pdf - CS150 Cache Checkpoint Dan Yeager Daiwei Li James Parker Current Architecture Block Rams ● Essentially single write port dual read

lec19_cp4.pdf - CS150 Cache Checkpoint Dan Yeager Daiwei Li...

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)()CS° ± )()Cache )()Checkpoint *)*Dan Yeager² *)*Daiwei 2Li² 0James Parker
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)()Current '&'Architecture% ('(Block Rams Essentially single write port, dual read ports Pros: Simple Fast (1 cycle) Allows us to load programs into IMEM using SW Cons: Max 5MB block ram space
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+*+Expanding Memory Images from DDCA ³*)*D*)*DR´µ
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*)*D*)*DR´ ¶ ('(Basic ./Idea Same interface: Dual read read ports for I & D Writes now more complicated (to be discussed) M./IPS *)*D*)*DR´ ./I )()Cache *)*D )()Cache
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)()Concurrency Write 0xBAADF00D to ICache 0x00000000 Write 0xDEADBEEF to DCache 0x00000000 Caches not concurrent! M./IPS *)*D*)*DR´ ./I )()Cache *)*D )()Cache
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)()Concurrency Solution 1. Writing a new program: Write to I & D simultaneously Hardware enforced Concurrency enforced 2. D-cache loads and stores: Don't overwrite the program space SW enforced OK if not concurrent D D D D D I I I I
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('(B./IOS Write to I & D Cache simultaneously Run bios out of block ram Like I/D mem from last checkpoint M./IPS *)*D*)*DR´ ./I )()Cache *)*D )()Cache ('(B./IOS
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Memory Map *)*Device R·W Top Nibble '&'Address Type
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