hw3.pdf - UNIVERSITY OF CALIFORNIA BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework#3 Due

# hw3.pdf - UNIVERSITY OF CALIFORNIA BERKELEY College of...

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UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #3 EECS 150 Due Thursday, September 22, 5pm, 240 Cory drop box. 1. An “N:M compressor” creates an M-bit binary-weighted output that represents the N-bit unit- weighted input. For example, a full adder represents A+B+Cin as R+Cout, and thus implements a 3:2 compressor. For this problem, you will create a 5:3 compressor. The five equally-weighted input bits are represented by 3 binary-encoded outputs. a. Download the HW3 Verilog project (instructions at the end of this document). b. Implement a 5:3 compressor in “Compressor53.v”. A skeleton is provided; do not change the interface. c. Write a self-checking testbench for the 5:3 compressor in “HW3Testbench.v”. Complete the “Compressor53Test.input” test vector file containing all 32 test cases; see DDCA Section 4.8 – Testbenches for an example. Please edit the existing file so as not to break the simulation script. d. Simulate the circuit and show that it works. e. Introduce an error in the test vector file and show that the testbench reports a mismatch. 2. DDCA 1.64 3. Logic design: a. Derive the logic function for the gate shown below: b. What type of gate is this?

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