lec12-timing.pdf - EECS150 Digital Design Lecture 12 – Timing(I October 4 2011 Elad Alon Electrical Engineering and Computer Sciences University of

lec12-timing.pdf - EECS150 Digital Design Lecture 12 –...

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10/4/2011 1 Fall 2011 EECS150 Lecture 12 Page 1 EECS150 - Digital Design Lecture 12 – Timing (I) October 4, 2011 Elad Alon Electrical Engineering and Computer Sciences University of California, Berkeley Fall 2011 EECS150 Lecture 12 Page 2 Announcements Homework #5 due Thursday Homework #6 out Thursday Due next Thursday Project checkpoint #1 due this week Project checkpoint #2 due next week
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10/4/2011 2 Fall 2011 EECS150 Lecture 12 Page 3 Agenda Why do we care about timing? How do we determine timing? Basic restriction on clock period Clock skew Fall 2011 EECS150 Lecture 12 Page 4
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10/4/2011 3 Fall 2011 EECS150 Lecture 12 Page 5 Fall 2011 EECS150 Lecture 12 Page 6 Gate Delay is the Result of Cascading Cascaded gates: “transfer curve” for inverter.
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10/4/2011 4 Fall 2011 EECS150 Lecture 12 Page 7 Fall 2011 EECS150 Lecture 12 Page 8 Wire Delay In general, wires behave as “transmission lines”: signal wave-front moves close to the speed of light ~1ft/ns Time from source to destination is called the “transit time”.
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