Chapter_04-2_pipeline.ppt - PIPELINE Chapter 4 — The Processor — 1 Pipelined laundry overlapping execution Parallelism improves performance Quiz

Chapter_04-2_pipeline.ppt - PIPELINE Chapter 4 — The...

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PIPELINE Chapter 4 — The Processor — 1
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Chapter 4 — The Processor — 2 Pipelining Analogy Pipelined laundry: overlapping execution Parallelism improves performance § 4 . 5 A n O v e r v i e w o f P i p e l i n i n g Quiz What is the improvement of the throughput? 8hr / 3.5hr = 2.3 What is the improvement of the response time (for each user)? No change
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Chapter 4 — The Processor — 3 Pipelining Analogy If different components take different time units to complete (e.g., 30, 40, 10, 10 mins respectively) § 4 . 5 A n O v e r v i e w o f P i p e l i n i n g Quiz What is the minimal clock period in this pipeline? 40 mins What is the improvement of the throughput? 360min / 280min = 1.29 The efficiency of the pipeline is limited by the slowest stage
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Chapter 4 — The Processor — 4 Pipeline Speedup If all stages are balanced i.e., all take the same time Time between instructions pipelined = Time between instructions nonpipelined Number of stages If not balanced, speedup is less Speedup due to increased throughput Latency (time for each instruction) does not decrease
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CPU Overview Chapter 4 — The Processor — 5 How to divide each instruction into small stages?
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Chapter 4 — The Processor — 6 MIPS Pipeline Five stages, one step per stage 1. IF: Instruction fetch from memory 2. ID: Instruction decode & register read 3. EX: Execute operation or calculate address 4. MEM: Access memory operand 5. WB: Write result back to register
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Chapter 4 — The Processor — 7 MIPS Pipelined Datapath § 4 . 6 P i p e l i n e d D a t a p a t h a n d C o n t r o l
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Chapter 4 — The Processor — 8 Pipeline registers Need registers between stages To hold information produced in previous cycle
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Chapter 4 — The Processor — 9 Pipeline Performance Assume time for stages is 100ps for register read or write 200ps for other stages Compare pipelined datapath with single-cycle datapath Instr Instr fetch Register read ALU op Memory access Register write Total time lw 200ps 100 ps 200ps 200ps 100 ps 800ps sw 200ps 100 ps 200ps 200ps 700ps R-format 200ps 100 ps 200ps 100 ps 600ps beq 200ps 100 ps 200ps 500ps
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Chapter 4 — The Processor — 10 Pipeline Performance Single-cycle (T c = 800ps) Pipelined (T c = 200ps)
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Resource are shared Chapter 4 — The Processor — 11
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Multi-Execution Steps Chapter 4 — The Processor — 12 Stage Action for R-type instructions Action for memory-reference instructions Action for branches Action for jumps 1 IR = Memory[PC] PC = PC + 4 2 A = Reg [IR[25-21]] B = Reg [IR[20-16]] 3 ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] II (IR[15-0]) PC = PC+ (IR[25-0]<<2) sign-ext(IR[15-0])<<2 4 Reg[IR[15-11]] =ALUOut Load: MDR = Memory[ALUOut] or Store: Memory [ALUOut] = B 5 Load: Reg[IR[20-16]] = MDR Generate control signals
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Chapter 4 — The Processor — 13 Pipelining and ISA Design MIPS ISA designed for pipelining All instructions are 32-bits Easier to fetch in one cycle c.f. x86: 1- to 17-byte instructions Few and regular instruction formats Can decode and read registers in one step
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  • Fall '18
  • 鄭雅軒

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