Chapter_04-1_SingCycCPU.ppt - COMPUTER ORGANIZATION AND DESIGN 5 Edition th The Hardware/Software Interface Chapter 4 The Processor §4.1 Introduction

Chapter_04-1_SingCycCPU.ppt - COMPUTER ORGANIZATION AND...

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COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor
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Chapter 4 — The Processor — 2 Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified version A more realistic pipelined version Simple subset, shows most aspects Memory reference: lw , sw Arithmetic/logical: add , sub , and , or , slt Control transfer: beq , j § 4 . 1 I n t r o d u c t i o n
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Chapter 4 — The Processor — 3 Instruction Execution PC instruction memory, fetch instruction Register numbers register file, read registers Depending on instruction class Use ALU to calculate Arithmetic result Memory address for load/store Branch target address Access data memory for load/store PC target address or PC + 4
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Chapter 4 — The Processor — 4 CPU Overview
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Chapter 4 — The Processor — 5 Multiplexers Can’t just join wires together Use multiplexers
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Chapter 4 — The Processor — 6 Control
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Chapter 4 — The Processor — 7 Logic Design Basics § 4 . 2 L o g i c D e s i g n C o n v e n t i o n s Information encoded in binary Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses Two types of elements: Combinational element Operate on data Output is a function of input State (sequential) elements Made up of combinational element and memory element to store information Output is a function of input and previous state
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Chapter 4 — The Processor — 8 Combinational Elements AND-gate Y = A & B A B Y I0 I1 Y M u x S Multiplexer Y = S ? I1 : I0 A B Y + A B Y ALU F Adder Y = A + B Arithmetic/Logic Unit Y = F(A, B)
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Chapter 4 — The Processor — 9 Sequential Elements Register: stores data in a circuit Uses a clock signal to determine when to update the stored value (Positive) Edge-triggered: update when Clk changes from 0 to 1 D Clk Q Clk D Q
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Chapter 4 — The Processor — 10 Sequential Elements Register with write control Only updates on clock edge when write control input is 1 Used when stored value is required later D Clk Q Write Write D Q Clk
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Chapter 4 — The Processor — 11 Clocking Methodology Combinational logic transforms data during clock cycles Between clock edges Input from state elements, output to state element Longest delay determines clock period
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  • Fall '18
  • 鄭雅軒

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