Chapter_04-3_hazard.ppt - Hazards Situations that prevent starting the next instruction in the next cycle Types of hazards Structure hazards Data hazard

Chapter_04-3_hazard.ppt - Hazards Situations that prevent...

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Chapter 4 — The Processor — 1 Hazards Situations that prevent starting the next instruction in the next cycle Types of hazards Structure hazards A required resource is busy Making instructions have the same length may solve the problem Data hazard Need to wait for previous instruction to complete its data read/write Control hazard Deciding on control action depends on previous instruction Can always resolve hazards by waiting
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Chapter 4 — The Processor — 2 Data Hazards An instruction depends on completion of data access by a previous instruction add $s0 , $t0, $t1 sub $t2, $s0 , $t3 Read After Write (RAW) hazard
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Types of Data Hazards Three types: (First inst.: i1; second inst.: i2) RAW (read after write): i2 tries to read operand before i1 writes it WAR (write after read): i2 tries to write operand before i1 reads it Can’t happen in MIPS 5-stage pipeline WAW (write after write): i2 tries to write operand before i1 writes it Leaves wrong result ( i1’s not i2’s); occur only in pipelines that write in more than one stage Can’t happen in MIPS 5-stage pipeline Chapter 4 — The Processor — 3
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Data Hazard Illustrated Chapter 4 — The Processor — 4 IF ID EX MEM WB IF ID EX Mem RAW (read after write) Data Hazard WAW Data Hazard (write after write) IF ID EX MEM WB WAR Data Hazard (write after read) IF ID EX MEM WB IF ID EX MEM WB time
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Handling Data Hazards Use simple, fixed designs Eliminate WAR by always fetching operands early (ID) in pipeline Eliminate WAW by doing all write backs in order (last stage, static) These features have a lot to do with ISA design Internal forwarding in register file: Write in first half of clock and read in second half Detect and resolve remaining ones Compiler inserts NOP (software solution) Forward (hardware solution) Stall (hardware solution) Chapter 4 — The Processor — 5
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Chapter 4 — The Processor — 6 Data Hazards in ALU Instructions Consider this sequence: sub $2 ,$1,$3 and $12, $2 ,$5 or $13,$6, $2 add $14, $2 , $2 sw $15,100( $2 ) We can resolve hazards with forwarding How do we detect when to forward? § 4 . 7 D a t a H a z a r d s : F o r w a r d i n g v s . S t a l l i n g
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Chapter 4 — The Processor — 7 Forwarding (aka Bypassing) Use result when it is computed Don’t wait for it to be stored in a register Requires extra connections in the datapath Shading: the element is used Shading on the right half: the element is read in that stage Shading of the left half: the element is written in that stage
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Chapter 4 — The Processor — 8 Dependencies & Forwarding 1. The value in $2 is 10 in the beginning of CC 5 2. It is updated to -20 during CC 5 3. A clock cycle has to be long enough to reflect the update
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ALU and Pipeline w/o Forwarding Chapter 4 — The Processor — 9
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Chapter 4 — The Processor — 10 Forwarding Paths
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Chapter 4 — The Processor — 11 Detecting the Need to Forward (1/2) Pass register numbers along pipeline e.g., ID/EX.RegisterRs = register number for Rs
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  • Fall '18
  • 鄭雅軒

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