EE658_Fall2019_HW1.pdf - EE658 Diagnosis and Design of Reliable Digital Systems Prof Moe Tabar Fall-2019 Assignment 1 Exercises Exercise 1 Define the

EE658_Fall2019_HW1.pdf - EE658 Diagnosis and Design of...

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EE658 - Diagnosis and Design of Reliable Digital Systems Prof. Moe Tabar Fall-2019 Assignment 1 Exercises Exercise 1. Define the following terms and answer the question: (a) Design error (b) Fabrication defects Which process (verification or test) is supposed to catch each one of these problems? What is the difference between test and verification? Exercise 2. In a computer program, software bug will cause the program to behave in unintended ways. In hardware verification and testing, which of the following problems is analogous to the bug problem in a software: (a) Design error (b) Fabrication defects (c) Physical failure Explain your answer. Also define and compare all items above. Exercise 3. What is fault modeling? List some commonly used fault models. Do we always want to design fault model to precisely mimic the real defects? Briefly explain. Exercise 4. True or False? (a) Any fault is a defect (b) Any defect is a fault (c) Any fault causes an error in computation (d) A circuit has an error iff (if and only if) it has a signal with wrong logic value permanently Exercise 5. Assume a PCB contains 4 chips. The probability of a chip being good is p, and the probability that the board has only good chips is P. (a) Whats the smallest value of p so that p > 0 . 856 (b) Whats the largest value of p so that p > 0 . 856 (c) Whats the largest value of p so that p < 0 . 856 Exercise 6. In the notes we say that the defect level ( DL ) is given by the equation: DL 1 - Y (1 - DC ) (1) where DC is the defect coverage. (a) Assuming the yield is 0.85, what is the smallest value of DC to insure a DL of at most 50 bad chips per million? (b) Give an intuitive explanation for this mathematical relationship. Exercise 7. Write at least 4 different functional tests for a clocked edge-triggered DFF in a standard cell library. USC - Ming Hsieh Department of Electrical and Computer Engineering 1 of 7
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EE658 - Diagnosis and Design of Reliable Digital Systems Prof. Moe Tabar Fall-2019 Assignment 1 Exercise 8. What is burn-in test? What’s the relation between burn-in test and bath-tub curve? Exercise 9. Given a faulty 3-input NAND gate, its behavior is exactly like a 2-input NAND gate (it doesnt care about the value of one of its inputs). Please analyze the possible causes under the following 3 fault models. (a) SSA (Single Stuck at) model (b) Wired OR short model (c) Stuck-open/stuck-on transistor model Exercise 10. Consider an adder circuit made up of full-adders, only consider s-a-1 and s-a-0 faults at its input and output terminals. For a single full adder, determine a minimal number of test patterns that will detect all detectable SSAFs on its I/O. What if its an n-bit ripple carry adder, could you still find a set of test patterns that detect all detectable SSAFs on its I/O? Exercise 11. Is traditional I ddq test still effective for deep sub-micron technologies? How it will affect yield loss? Briefly explain.
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