EE658_Fall2019_HW2.pdf - EE658 Diagnosis and Design of Reliable Digital Systems Prof Moe Tabar Fall-2019 Assignment 2 Exercises Exercise 1 Define the

EE658_Fall2019_HW2.pdf - EE658 Diagnosis and Design of...

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EE658 - Diagnosis and Design of Reliable Digital Systems Prof. Moe Tabar Fall-2019 Assignment 2 Exercises Exercise 1. Define the following terms: (a) Transport Delay, Inertial Delay, ambiguous delay, rise and fall delay (b) Parallel fault simulation vs. deductive fault simulation (c) Static hazard vs. dynamic Hazard (d) Compiled simulation vs event-driven simulation (e) Two-pass algorithm - true event scheduling vs. false event scheduling. Exercise 2. Answer the following questions: (a) What are PVT corners? How we can use them for testing delay in chips? (b) Compare memory usage of deductive fault simulator, serial fault simulator and concurrent fault simulator. (c) Given the knowledge of checkpoints, whats an upper bound number of tests we need to fully test a fanout-free circuit which has 15 inputs and 3 outputs? Exercise 3. Consider a combinational circuit is represented as logical function Z ( X ) where X is a vector of input values. A specific fault ( f ) will change the functionality of the circuit, and the new faulty circuit function is represented as Z f ( X ). What is the necessary and sufficient condition for test data T to detect this fault (present your answer in logical form)? Can you justify your answer in simple words, using terms ”activating the fault” and ”propagating the fault” ? Exercise 4. The Trojan Circuit Company (founded in Fall 2019) designed a new architecture for a fastap- proximate multiplier ( approx ).This circuit takes two floating points (32bit) and produces an 4bit value as output, while the previous design ( norm ) was a correct multiplier with 32bit FP output. The RTL team implemented the design (in Verilog). The logic synthesis team used the RTL and synthesized a gate-level netlist. The netlist is then handed to a test engineer. The test engineer compares and reports the test process of the approximate and exact (normal) FP multipliers using the same techniques and algorithms. The report mentions that the area (a good measurement of the number of logic cells) of the two designs are the same. (a) Do you expect the FC approx be higher or lower than the FC norm (briefly explain)? A synthesis team member mentioned that inputs and output are connected to registers, but it is possible to change the physical design in a way we can have access to the internal nodes of the block. (b) How this access can help us improve the FC? Can you justify your answer by using terms observability and controllability ? Exercise 5. Does the checkpoint theorem give us the smallest set of [email protected]? Follow these questions consid- ering the circuit shown in Fig. 5: (a) In total, how many [email protected] are in the circuit? (b) What about after applying the checkpoint theorem? (c) Can you find relations between the remaining [email protected] to come up with a smaller fault-list? USC - Ming Hsieh Department of Electrical and Computer Engineering 1 of 13
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EE658 - Diagnosis and Design of Reliable Digital Systems Prof. Moe Tabar Fall-2019 Assignment 2 Figure 1: A reconvergent combinational circuit used to examine the relationship of checkpoint theorem and [email protected] list.
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