Lecture 3. Defects, Faults.pdf - EE 658 Diagnosis and Design of Reliable Digital Systems Lecture 3 Defects Faults and their models and associated

# Lecture 3. Defects, Faults.pdf - EE 658 Diagnosis and...

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EE 658 Diagnosis and Design of Reliable Digital Systems University of Southern California Viterbi School of Engineering Ming Hsieh Dept. of Electrical Engineering Moe Tabar Fall 2019 Lecture 3: Defects, Faults and their models and associated processes References: Dr. Breuer’s lecture slides, books listed in the syllabus, and online resources
The test generation process Dr. Moe Tabar - EE 658 2 Design for testability rule check Design for testability evaluation (measures) Construct statistics and diagnostic data Redesign? Preprocessing of faults: equivalence, dominance, ... Translate to ATE language \$’s < K1; % detection < K2; CPU time < K3? Fault simulation: Z 1 , Z 2 , ... Good circuit simulation: compute Z and check for races and hazards Manual (functional tests) Algorithmic Special structures, e.g. PLAs Heuristic Random Standard tests, e.g. RAMs and ROMs Generating tests sequences •Circuit description •Constraints •Goals Redesig n Y N N Y
What you should learn from this module ص What is a fault model ص Various examples of fault models ص Characteristics of faults ص Detection of faults in combinational and sequential circuits ص Controlling value ص Redundancy ص Synchronizing sequence ص Fault equivalence ص Fault dominance ص Checkpoints ص Masking Dr. Moe Tabar - EE 658 3
Outline 3.0 Defects, Faults and their models and associated processes 3.1 Fault models and modeling 3.1.1 Characteristics of faults models 3.1.2 Classic targeted structural models 3.2 Fault detection and redundancy 3.3 Sequential circuits 3.4 Fault equivalence and dominance 3.4.1 Fault equivalence 3.4.2 Fault dominance 3.4.3 Pruning and fault collapsing 3.5 Multiple stuck-at faults 3.6 Fault coverage and defect level 3.7 Yield loss model 3.8 Critical area 3.9 Miscellaneous results 3.10 Summary Dr. Moe Tabar - EE 658 4
3.1 Fault models and modeling ܶ A fault model is a “high level” abstraction or representation of physical defects. Such models are used in simulators and test generators. ܶ Fault models deal with several aspects (ramifications) of a defect, such as a change in logic function , timing (delay) and circuit topology (a short). For example, the behavioral aspects of an “open” may be “equivalent,” in a logical sense, to a wire always appearing to be at the value zero, referred to as “stuck-at-0” and denoted as SA-0. Dr. Moe Tabar - EE 658 5
Developing fault models Dr. Moe Tabar - EE 658 6 ܶ To determine “realistic” faults and fault models, first study typical defect analysis reports . ;:hen look at typical layout . Try to correlate the two. (This is called Inductive Fault Analysis.) Then look at the transistor level circuit represented by the layout. Determine the behavioral effect of the defect on the circuit. Then, try to encapsulate this behavior at a higher level of abstraction, such as the gate or VHDL/Verilog level. This results in a fault model .
3.1.1 Characteristics of faults models ص Explicit vs. implicit ص Structural vs. functional ص Permanent vs. intermittent vs. transient ص Single vs. multiple ص Impact on timing, logic and/or topology Dr. Moe Tabar - EE 658 7

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