Homework5 - A 3 5 V 2 V 0 V 800 A -2 V 0 V 0 V 72 A 4 -4 V...

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UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Dept. of Electrical Engineering and Computer Sciences Problem Set #5 Due Tuesday, March 7, 2006. EE 105 Spring 2006 1. Various NMOS and PMOS transistors are measured in operation, as shown in the following table. For each transistor, fill out the table. (Neglect channel length modulation and body effect) Transistor V S V G V D I D Type Mode μ C ox W/L V t 0 V 2 V 5 V 100 μ A Saturation 1 0 V 3 V 5 V 400 μ A NMOS Saturation 200 μ A/V 2 1 V 5 V 3 V - 4.5 V 50 μ A 2 5 V 2 V - 0.5 V 450 μ A 5 V 3 V 4 V 200
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Unformatted text preview: A 3 5 V 2 V 0 V 800 A -2 V 0 V 0 V 72 A 4 -4 V 0 V -3 V 270 A 2. For the following circuit, find the drain voltage V D for each case. (MOS in saturation) W / L = 10 n C ox = 20 A/V 2 V Tn = 2 V n = 0.05 V-1 n = 0 R = 20 k a) V dd = 10 V, V G = 3 V b) V dd = 20 V, V G = 3 V c) V dd = 20 V, V G = 4 V 3. For the following circuits, find the labeled currents and voltages ( I d and V d ). a) b) For NMOS and PMOS, W / L = 30 m/10 m n C ox = 50 A/V 2 p C ox = 20 A/V 2 | V T | = 1 V = 0 = 0...
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This note was uploaded on 04/01/2008 for the course EECS 105 taught by Professor Mingwu during the Spring '06 term at University of California, Berkeley.

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