Computer Organization and Design: The Hardware/Software Interface

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CS152 Spring ’99 Midterm II Page 1 University of California, Berkeley College of Engineering Computer Science Division EECS Spring 1999 John Kubiatowicz Midterm II Solutions April 21, 1999 CS152 Computer Architecture and Engineering Your Name: Solution SID Number: Discussion Section: Problem Possible Score 1 20 2 30 3 25 4 25 Total
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CS152 Spring ’99 Midterm II Page 2 [ This page left for π ] 3.141592653589793238462643383279502884197169399375105820974944
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CS152 Spring ’99 Midterm II Page 3 Problem 1: Memory Hierarchy Problem 1a: Below is a series of memory read references set to a cache. The cache holds 128 bytes total. It has 2-word blocks (i.e. 64bits), is 2-way set associative, and uses a least-recently-used replacement policy. Assume that the cache is initially empty. Classify each memory references as a hit or a miss. Identify each cache miss as either compulsory, conflict, or capacity. One example is shown below. Feel free to use space in the margin as scratch. Bit Pattern Address Hit/Miss? Miss Type? 00 000 111 0x7 Miss Compulsory 01 001 101 0x4D Miss Compulsory 00 101 010 0x2A Miss Compulsory 01 111 001 0x79 Miss Compulsory 10 101 011 0xAB Miss Compulsory 11 001 110 0xCE Miss Compulsory 00 101 110 0x2E Hit N/A 01 001 011 0x4B Hit N/A 01 101 101 0x6D Miss Compulsory 10 001 010 0x8A Miss Compulsory 10 101 111 0xAF Miss Conflict 00 101 001 0x29 Miss Conflict 11 001 000 0xC8 Miss Conflict 11 001 110 0xCE Hit N/A 01 101 010 0x6A Miss Conflict Tag index Offset (ignore) Ans: The trick with this type of cache simulation is the split the address into bit fields. Each cache block is 8 bytes offset is 3 bits. This is the lowest 3 bits of the address, and should be completely ignored. The total blocks in the cache is 128 bytes/8 bytes=16 blocks. Since the cache is 2-way set associative, this means that the cache index selects among 16/2 = 8 blocks. So, index is 3 bits. Finally, the remaining two bits at the top are tag bits. Problem 1b: Calculate the miss rate and hit rate. Miss Rate = 12/15 = 80% Hit Rate = 3/15 = 20%
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CS152 Spring ’99 Midterm II Page 4 Problem 1c: Suppose you have a 32-bit processor, with a virtual-memory page-size of 16K. The data cache is 32K in size with 32-byte cache blocks. Finally, your TLB has 4 entries. Assume that you wish to do TLB lookups in parallel with cache lookups. Draw a block diagram of the data cache and TLB organization, showing a virtual address as input and both a physical address and data as output. Include cache hit and TLB hit output signals. Include as much information about the internals of the TLB and cache organization as possible. Include, among other things, all of the comparators in the system and any muxes as well. You can indicate RAM as with a simple block, but make sure to label address widths and data widths. Make sure to use abstraction in your diagram so that we can understand it. Label the function of various blocks and the width of any buses.
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