Computer Organization and Design: The Hardware/Software Interface

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CS152 Spring ’99 Midterm II Page 1 University of California, Berkeley College of Engineering Computer Science Division EECS Spring 1999 John Kubiatowicz Midterm II April 21, 1999 CS152 Computer Architecture and Engineering Your Name: Solution SID Number: Discussion Section: Problem Possible Score 12 0 23 0 32 5 42 5 Total
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CS152 Spring ’99 Midterm II Page 2 [ This page left for π ] 3.141592653589793238462643383279502884197169399375105820974944
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CS152 Spring ’99 Midterm II Page 3 Problem 1: Memory Hierarchy Problem 1a: Below is a series of memory read references set to a cache. The cache holds 128 bytes total. It has 2-word blocks (i.e. 64bits), is 2-way set associative, and uses a least-recently-used replacement policy. Assume that the cache is initially empty. Classify each memory references as a hit or a miss. Identify each cache miss as either compulsory, conflict, or capacity. One example is shown below. Feel free to use space in the margin as scratch. Address Hit/Miss? Miss Type? 0x7 Miss Compulsory 0x4D 0x2A 0x79 0xAB 0xCE 0x2E 0x4B 0x6D 0x8A 0xAF 0x29 0xC8 0xCE 0x6A Problem 1b:
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CS152 Spring ’99 Midterm II Page 4 Problem 1c: Suppose you have a 32-bit processor, with a virtual-memory page-size of 16K. The data cache is 32K in size with 32-byte cache blocks. Finally, your TLB has 4 entries. Assume that you wish to do TLB lookups in parallel with cache lookups. Draw a block diagram of the data cache and TLB organization, showing a virtual address as input and both a physical address and data as output. Include cache hit and TLB hit output signals. Include as much information about the internals of the TLB and cache organization as possible. Include, among other things, all of the comparators in the system and any muxes as well. You can indicate RAM as with a simple block, but make sure to label address widths and data widths. Make sure to use abstraction in your diagram so that we can understand it. Label the function of various blocks and the width of any buses.
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CS152 Spring ’99 Midterm II Page 5 Now, assume the following instruction mix: Loads: 20%, Stores: 15%, Integer: 29%, Floating-Point: 16% Branches: 20% Assume that you have a memory-hierarchy consisting of 2-levels of cache, 1 level of DRAM, and a DISK. The following parameters are appropriate. Assume a 200MHz processor: Component Hit Time Miss Rate Block Size First-Level Cache 1 cycle 5% Data 1% Instructions 32 bytes Second-Level Cache 10 cycles + 1 cycle/64bits 3% 128 bytes DRAM 100ns+ 25ns/8 bytes 1% 16K bytes DISK 50ms + 20ns/byte 0% 16K bytes In addition, assume that there is a TLB which misses 0.1% of the time on data (doesn’t miss on instructions) and which has a fill penalty of 50 cycles. Problem 1d: What is the average memory access time for Instructions? For Data?
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CS152 Spring ’99 Midterm II Page 6 Problem 2: Multicycle Polynomial Multiply The VAX architecture from Digital Equipment Corporation was well known for its complex instruction set. One instruction that was often cited was the polynomial multiply instruction.
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This homework help was uploaded on 01/29/2008 for the course CS 152 taught by Professor Kubiatowicz during the Spring '04 term at University of California, Berkeley.

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