Computer Organization and Design: The Hardware/Software Interface

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Spring 1999 John Kubiatowicz Homework Quiz (HW #6) April 19, 1999 CS152 Computer Architecture and Engineering This quiz covers one of the problems from homework #6. Good Luck! Your Name: SID Number: Discussion Section: Total:
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3 Cache organization Your company has an application that must be run as fast as possible. The hardware division of your company has come up with three separate first-level cache configurations: Machine I: Direct-mapped with one-word blocks Machine II: Direct-mapped with four-word blocks Machine III: Two-way set associative with four-word blocks For these machines, the cache fill penalty is 4 cycles + 1 cycle for each word. You did some experiments and measured the following instruction mix for the application:
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Unformatted text preview: Branch: 16%, Load: 15%, Store: 10%, Float Insts: 20%, Integer: 39% Further, through a hardware cache monitor, you measured the following miss rates: • Machine I: Instruction miss rate: 4%; Data miss rate: 20% • Machine II: Instruction miss rate: 2%; Data miss rate: 16% • Machine III: Instruction miss rate: 1.5%; Data miss rate: 14% Finally, the total CPI measured with Machine I is 3.0. 1. Which of these machines spends the most time waiting for memory? Justify your answer: 2. Suppose we increase the associativity of Cache III (keeping the block-size constant). In this new configuration, the instruction miss rate goes to zero. Further, we measure a total CPI of 2.71. What is the data miss rate?...
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