Computer Organization and Design: The Hardware/Software Interface

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Spring 1999 John Kubiatowicz Homework Quiz (HW #5) April 5, 1999 CS152 Computer Architecture and Engineering This quiz covers one of the problems from homework #5. Good Luck! Your Name: SID Number: Discussion Section: Total:
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3 In problem 6.26, you were asked to consider a pipeline which does not support a delayed branch . Figure 6.51 from one of the printings of the book is reproduced on the previous page. 1. In this datapath, how many instructions must be “flushed” out of the pipeline when a branch is taken? Explain. One. The comparison for the branch is performed in the Decode stage, so there is only one additional instruction in the pipeline at that time. 2. What must be in the “Control” oval in order to support flushing (i.e. when does it decide to assert IF.Flush)? What exactly does the “IF.Flush” signal do? The “Control” oval must flush if A. There is a branch in the decode register, IF/ID.
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  • Spring '04
  • Kubiatowicz
  • Computer Architecture, Central processing unit, IF/ID register, John Kubiatowicz, ID/Ex Register, Berkeley College of Engineering Computer Science Division

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