sp99 midterm1

# Computer Organization and Design: The Hardware/Software Interface

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Spring 1999 John Kubiatowicz Midterm I March 3, 1999 CS152 Computer Architecture and Engineering Your Name: SID Number: Discussion Section: Problem Possible Score 1 15 2 15 3 20 4 20 5 30 Total

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3 Problem 1: Performance Problem 1a : Name the three principle components of runtime that we discussed in class. How do they combine to yield runtime? Now, you have analyzed a benchmark that runs on your company’s processor. This processor runs at 300MHz and has the following characteristics: Instruction Type Frequency (%) Cycles Arithmetic and logical 40 1 Load and Store 30 2 Branches 20 3 Floating Point 10 5 Your company is considering a cheaper, lower-performance version of the processor. Their plan is to remove some of the floating-point hardware to reduce the die size. The wafer on which the chip is produced has a diameter of 10cm, a cost of \$2000, and a defect rate of 1 / (cm 2 ). The manufacturing process has an 80% wafer yield and a value of 2 for α . Here are some equations that you may find useful: The current procesor has a die size of 12mm × 12mm. The new chip has a die size of 10mm × 10mm, and floating point instructions will take 12 cycles to execute. Problem 1b : What is the CPI and MIPS rating of the original processor? ( 29 area die 2 diameter wafer area die diameter/2 wafer dies/wafer × × π - × π = 2 α - α × + × = area die area unit per defects 1 yield wafer yield die

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4 Problem 1c: What is the CPI and MIPS rating of the new processor? Problem 1d: What is the original cost per (working) processor? Problem 1e: What is the new cost per (working) processor? Problem 1f: What is the improvement (if any) in price per performance?
5 Problem 2: Delay For a Full Adder A key component of an ALU is a full adder. A symbol for a full adder is: Problem 2a: Implement a full adder using as few 2-input AND, OR, and XOR gates as possible. Keep in mind that the Carry In signal may arrive much later than the A or B inputs. Thus, optimize your design (if possible) to have as few gates between Carry In and the two outputs as possible: Full Adder A B S C in C out

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6 Assume the following characteristics for the gates: AND: Input load: 150fF, Propagation delay: TPlh=0.2ns, TPhl=0.5ns, Load-Dependent delay: TPlhf=.0020ns, TPhlf=.0021ns OR: Input load: 100fF Propagation delay: TPlh=0.5ns, TPhl=0.2ns Load-Dependent delay: TPlhf=.0020ns, TPhlf=.0021ns XOR: Input load: 200fF, Propagation delay: TPlh=.8ns, TPhl=.8ns Load-Dependent delay: TPlhf=.0040ns,TPhlf=.0042ns
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