lecture4 - EECS 312 1 Lecture 4 Digital Circuit Metrics...

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Unformatted text preview: EECS 312 1 Lecture 4 Digital Circuit Metrics & CMOS Inverter EECS 312 Reading: 1.3, 5.1 EECS 312 2 Last Time Capacitances Inverter: First look SPICE models Rely on these complex descriptions of MOSFETs to simulate large circuits EECS 312 3 Lecture Outline General digital design metrics: How we evaluate device performance Fabrication EECS 312 4 Key Design Metrics For the entire class, we will focus on: Functionality (must have this) Reliability , Robustness Area (this relates to cost, complexity) Fewer transistors to implement a function is desired Performance Speed (delay) Power and energy EECS 312 5 The Ideal Gate V in V out g= R i = R o = 0 Immediate transition from high to low; maximized noise margins V OH = V dd , V OL = 0 High input resistance prevents DC current Low output resistance translates to small delays and good noise immunity V dd gain EECS 312 6 DC Operation: Voltage Transfer Characteristic (VTC) V(x) V(y) V OH V OL V M V OH V OL f V(y)=V(x) Switching Threshold Nominal Voltage Levels V(y) V(x) V M : V in = V out Switching threshold of the gate EECS 312 7 Mapping between analog and digital signals "1" "0" V OH V IH V IL V OL Undefined Region V(x) V(y) V OH V OL V IH V IL Slope = -1 Slope = -1 EECS 312 8 Definition of Noise Margins V IH V IL Undefined Region "1" "0" V OH V OL NM H NM L Gate Output Gate Input Noise Margin High Noise Margin Low Gate M Gate M+1 EECS 312 9 Example Noise Sources in Digital ICs V DD v ( t ) Inductive coupling Capacitive coupling Power/ground/substrate noise EECS 312...
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lecture4 - EECS 312 1 Lecture 4 Digital Circuit Metrics...

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