lecture5 - EECS 312 1 Lecture 5: CMOS Inverter EECS 312...

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Unformatted text preview: EECS 312 1 Lecture 5: CMOS Inverter EECS 312 Reading: 5.3.1, 5.3.2 EECS 312 2 Last Time Important metrics for digital circuits are: Delay (50% and 10-90% are key), power/energy, area (cost), reliability Functionality is assumed Voltage transfer characteristics show input- output relationships VTCs describe the static behavior of a gate CMOS inverter is the basic building block we will start with EECS 312 3 Lecture Outline Introduce the CMOS inverter, DC analysis Switch-based model; very useful for both steady-state (DC) and transient analysis VTC properties and analysis Start looking at delay analysis EECS 312 4 Introduction to the CMOS Inverter EECS 312 5 The CMOS Inverter: A First Glance V DD V in V out C L EECS 312 6 CMOS Inverter Layout In Out In V DD Out Metal1 GND NMOS PMOS Polysilicon Were not doing layout in 312 but useful to recognize EECS 312 7 Switch Model of MOS Transistor R on |V GS | < |V T | |V GS | > |V T | |V GS | From V=IR, R on 1/I d EECS 312 8 CMOS Inverter: Steady State Response V DD V DD V in = 1 V out V in = 0 V out R eqn R eqp V OH = V DD V OL = 0 EECS 312 9 CMOS Inverter: Transient Response V DD V out V in = V DD R on C L t pHL = f(R on .C L ) = 0.69 R on C L t V out V DD R on C L 1 0.5 ln(0.5) 0.36 ln(2) EECS 312 10 General CMOS Properties Full rail-to-rail swing Maximizes noise margins (V OH , V OL ) Regardless of device sizes: ratioless logic Symmetrical VTC Depending on device sizing No static power dissipation No direct path between Vdd and GND at stable operating points (V in = V OL or V OH ) Very important for low-power applications EECS 312 11 CMOS Properties, cont....
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lecture5 - EECS 312 1 Lecture 5: CMOS Inverter EECS 312...

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