lecture10 - Lecture 10: Dynamic Logic Intro EECS 312...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
EECS 312 1 Lecture 10: Dynamic Logic Intro EECS 312 Reading: 6.2.3, 6.3.1, 6.3.2
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Lecture Overview EECS 312 2 • Finish up pass-transistor logic discussion • Dynamic logic introduction
Background image of page 2
Last Time EECS 312 3 Ratioed logic replaces the PUN of CMOS gates with a simpler load device, saving area Pseudo-NMOS uses a PMOS device with gate grounded Conflicting design requirements: – Keep PMOS small so V OL is close to zero – Keep PMOS large so t plh is fast Pass transistor logic – Use devices purely as switches to pass signals along – NMOS-only PTL suffers from a V th drop when passing a logic high – Solution 1 Æ use a CMOS transmission gate which passes good high and low values • Problem: much more area, need complementary inputs, slower – Solution 2 Æ add a feedback level restoring transistor to pull up to V dd
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Dynamic Circuit Definition EECS 312 4 •I n static circuits, the output is connected to either GND or V dd via a low resistance path at
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 04/01/2008 for the course EECS 312 taught by Professor Maharbiz during the Fall '07 term at University of Michigan.

Page1 / 14

lecture10 - Lecture 10: Dynamic Logic Intro EECS 312...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online