lecture9 - Lecture 9: Ratioed Logic and Pass-transistor...

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9/30/03 EECS312 1 Lecture 9: Ratioed Logic and Pass-transistor Logic EECS 312 Reading: 6.2.2, 6.2.3 Exclude pages 267-268 on DCVSL
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Last Time 9/30/03 EECS312 2 • Scaling theory – Systematic approach to shrinking devices such that power, delay, area all improve • Variability – Focused on process variation where device parameters fluctuate from instance to instance – Voltage levels and temperature can also change circuit peformance
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Lecture Overview 9/30/03 EECS312 3 • Alternative logic families to static CMOS – Ratioed logic – Pass-transistor logic – Their advantages and disadvantages
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Ratioed Logic 9/30/03 EECS312 4 V DD V SS PDN In 1 In 2 In 3 F R L Load V DD V SS In 1 In 2 In 3 F V DD V SS PDN In 1 In 2 In 3 F V SS PDN Resistive Depletion Load PMOS Load (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS V T < 0 Advantage of each of these is that they require fewer devices than static CMOS
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Ratioed Logic Overview 9/30/03 EECS312 5 V DD V SS PDN In 1 In 2 In 3 F R L Load Resistive • (N + load) transistors instead of 2N •V OH = V dd OL = R pdn / (R pdn + R L ) • Asymmetric response (rise/fall times) • Static power consumption (sometimes) •t plh = 0.69*R L *C L phl = 0.69*(R L || R pdn )*C L
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Active Loads 9/30/03 EECS312 6 V DD V SS In 1 In 2 In 3 F V DD V SS PDN In 1 In 2 In 3 F V SS PDN Depletion Load PMOS Load depletion load NMOS pseudo-NMOS V T < 0
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lecture9 - Lecture 9: Ratioed Logic and Pass-transistor...

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