This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: EECS 312 1 Lecture 6: CMOS Inverter, cont. EECS 312 Reading: 3.3.2, 5.4.1, 5.4.2 5.5.1, 5.5.2 EECS 312 2 Lecture Outline • Delay analysis – Equivalent resistance of devices – More details on capacitance calculations – Some CMOS inverter delay properties/studies EECS 312 3 Delay analysis EECS 312 4 Delay Analysis • Integrate the charging current provided by the MOSFET to the load – Current is highly nonlinear with terminal voltages (C L has only minor dependency on voltage, which we neglect) • We must use simplifications/approximations 1. Look at the driving transistor as a resistor 2. Look at the driving transistor as a constant current source ( ) ( ) dv v i v C t v v L p ∫ = 2 1 EECS 312 5 CMOS Delay: Resistive Model V DD V out V in = V DD R eq C L t pHL = f(R eq .C L ) = 0.69 R eq C L t V out V DD R eq C L 1 0.5 ln(2) 0.36 What is R eq ? EECS 312 6 Effective onresistance of a MOSFET I D V DS V GS = V DD V DD /2 V DD R R mid Key: assumes saturation regime throughout! Valid in modern devices This I dsat definition is different than ours ( ) ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ − − = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ − ≈ + = ∫ 2 with 9 7 1 4 3 ) 1 ( 2 / 1 2 ' ' ' 2 / ' Dsat Dsat th dd dsat dd dsat dd V V dsat dd eq V V V V L W k I V I V dV V I V V R dd dd λ λ R eq EECS 312 7 Rabaey’s definition The curve flattens at V dd > 1V Velocity saturation occurs, current increases for larger Efields are fairly small Key R eq trends: R eq is inversely proportional to W/L R eq is relatively insensitive to V dd b/c as V dd ⇓ , I d ⇓ but voltage swing also ⇓ 0.5 1 1.5 2 2.5 1 2 3 4 5 6 7 x 10 5 V DD (V) R eq (Ohm) EECS 312 8 CMOS Delay: Current Source Model V DD V in = V DD I av V out C L Let i(v) and C L (v) be a constant with respect to voltage ∫ = 2 1 v v av L p dv I C t Voltage swing across C L is from V dd to V dd /2 (50% delay) ( ) av dd L av dd dd L p I V C I V V C t 2 2 / = − = EECS 312 9 CMOS Delay: Current Source Model V DD V in = V DD I av V out C L Question: What is I av ? Answer: Look at IV curves I d is nearly I dsat through voltage swing I av ~ I dsat I d V ds EECS 312 10 Our Default Approach C L V dd I dsat C L V dd R eq = ( ) dsat dd dsat L dd L eq I V a I aC V C R 725 . 2 69 . = = a accounts for nonideality of MOSFET as current source (a ~ 0.9 for 50% delay) Looking at the system in both ways – a simple expression can be found for R eq dsat dd eq I V R 8 . = EECS 312 11 Equivalent Resistance for Rise/Fall Delays 50% delay is not the only important metric We need to linearize the device over a different voltage range to capture R eq for 1090% rise/fall delay Current source assumption becomes less valid Resulting resistance for 1090%: dsat dd I V R 55 ....
View
Full
Document
 Fall '07
 MAHARBIZ
 Integrated Circuit

Click to edit the document details