lecture7 - Lecture 7: Inverter Power & CMOS gates EECS...

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EECS 312 1 Lecture 7: Inverter Power & CMOS gates EECS 312 Reading: 6.2.1 (up to pg. 251) 4.4.3
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EECS 312 2 Lecture Overview • CMOS inverter power • CMOS gates – Part I: • Extend CMOS inverter concepts to arbitrary gate configurations • Topologies/static characteristics – Part II: • Delay and performance
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EECS 312 3 Power Components in CMOS • Dynamic power consumption (dominant) – Charging and discharging capacitances through devices • Short-circuit power (manageable) – Direct path between V dd and ground during switching transients • Static power (exponentially increasing) – Leakage currents exist and consume power when not switching
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EECS 312 4 Energy Consumption in CMOS Vin Vout C L Vdd Energy per transition: The book claims that power/energy is independent of device sizing (pg. 215 of text) Æ misleading since device sizes primarily determine C L Can reduce C L , V dd , and f to minimize power 2 0 0 0 ) ( dd L V out dd L out L dd dd vdd Vdd V C dv V C dt dt dv C V dt V t i E dd = = = =
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EECS 312 5 Reduced Swing Nodes We’ll see cases later where this is important
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EECS 312 6 Energy vs. Power Each transition on C L requires C L *V dd 2 of energy BUT 1/2 of this energy is lost (to heat) while the other half is stored ( or removed) on/from the capacitor For every transition, C*V dd 2 /2 of energy is consumed For every period (both a L Æ H and H Æ L transition on C L ), C*V dd 2 of energy is consumed Then, power = rate of energy consumption so: P dyn = C L * V dd 2 * f sw Where f sw is the frequency with which C L switches
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EECS 312 7 Switching Activity, α sw Let f sw = α sw * f clock since we usually know clock frequency of a design (e.g. 2 GHz Pentium 4) 0 < α sw < 1 For α sw = 0, the circuit never switches so no dynamic power is consumed For α sw = 1, the node switches as often as the clock (the circuit cannot switch more often than this) so f sw = f clock Most cases Æ somewhere in between Lower α sw = lower power Clock Output node α sw = 0.25
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EECS 312 8 Fundamental Tradeoff: Power vs. Delay
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EECS 312 9 Short-circuit Power During input switching, both NMOS and PMOS are ON for a small amount of a time Some current is “lost” – meaning it’s not used to charge/discharge the capacitor, but flows to the other supply rail
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EECS 312 10 Modeling of Short-Circuit Power Model the short-circuit current waveform as a triangle The area of this triangle is the charge lost to short-circuit current (Q sc ) P sc = Q sc * V dd * 2f sw Q sc = 0.5* t sc * I peak t sc ~ ((V dd –2V th )/V dd ) * (t in / 0.8) [Linear input assumption ] I peak Æ depends on device sizing, should occur around V in = V dd /2 (through PMOS during output H Æ L transition in this case) 2 occurrences per period
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EECS 312 11 Impact of rise/fall times on short- circuit currents V DD V out C L V in I SC ≈ 0 V DD V out C L V in I SC I MAX Large capacitive load Small capacitive load Most of the current is used to charge load cap.
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lecture7 - Lecture 7: Inverter Power &amp; CMOS gates EECS...

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