lecture8 - Lecture 8: Scaling + Process Variation EECS 312...

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EECS 312 1 Lecture 8: Scaling + Process Variation EECS 312 Reading: 6.2.1 (pgs 250-251), 3.4- 3.5, 5.6
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EECS 312 2 Last Time • Unlike inverters, there are multiple charge/discharge paths in complex gates – Must size devices according to worst-case paths, try to balance rise/fall delays – We can “collapse” series and parallel devices into a single effective MOSFET • A number of techniques to speed up gates exist – Re-ordering devices, progressive sizing, a few more shown next – Elmore delay concept helps us model gate delays with internal capacitances considered
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EECS 312 3 Lecture Overview • Two more techniques to design fast complex gates • Scaling theory – Systematic means of shrinking transistors to achieve better performance • Variation – Process, voltage, and temperature fluctuations
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EECS 312 4 Influence of Fan-In and Fan-Out on Delay V DD A B A B C D CD Fan-out Number of gates the output is connected to; C L grows linearly with Fan-out Fan-In: Quadratic Term due to: 1. Resistance increasing due to series devices 2. Capacitance increasing (internal) t p Fan-in 2 t p Fan-out
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EECS 312 5 t p as a function of Fan-In (NAND gate) t pLH t p (psec ) fan-in 0 250 500 750 1000 1250 2 4 6 8 10 12 14 16 t pHL quadratic linear t p t pHL t p t pLH Gates with fan-in greater than 4 should be avoided
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EECS 312 6 Fast Complex Gates - Design Techniques (1) • Transistor sizing; make all devices wider – OK as long as fan-out/wiring capacitance dominates • Progressive sizing In N C L C 3 C 2 C 1 In 1 In 2 In 3 M1 M2 M3 MN Distributed RC line M1 > M2 > M3 > … > MN (the device closest to the output is the smallest since it discharges the least capacitance)
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EECS 312 7 Fast Complex Gate - Design Techniques (2) • Transistor ordering C 2 C 1 In 1 In 2 In 3 M1 M2 M3 C L C 2 C 1 In 3 In 2 In 1 M1 M2 M3 C L
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lecture8 - Lecture 8: Scaling + Process Variation EECS 312...

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