lecture14 - Last Time Lecture 14 Sequential Elements(con't...

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EECS 312 1 Lecture 14: Sequential Elements (con’t) EECS 312 Reading: 7.1.1, 7.2-7.3.1 Exclude 7.2.4 EECS 312 2 Last Time • Sequential elements – Store data based on positive feedback or capacitive charge storage – Register and latch definitions • Topologies for: – Static Latches – Edge-triggered registers EECS 312 3 Lecture Overview • Registers EECS 312 4 Review: Writing into a Static Latch CLK CLK CLK D Q D CLK CLK D Converting into a MUX Forcing the state (can implement as NMOS-only) Use the clock as a decoupling signal that distinguishes between the transparent and opaque states
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EECS 312 5 Review: Storage Mechanisms D CLK CLK Q Dynamic (charge-based) CLK CLK CLK D Q Static EECS 312 6 Review: Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0 D Q 0 CLK 1 D Q In Clk Q Clk Q + = In Clk Q Clk Q + = EECS 312 7 Master-Slave (Edge-Triggered) Register 1 0 D CLK Q M Master 0 1 CLK Q Slave Q M Q D CLK Two opposite latches act to trigger on clock edge
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This note was uploaded on 04/01/2008 for the course EECS 312 taught by Professor Maharbiz during the Fall '07 term at University of Michigan.

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lecture14 - Last Time Lecture 14 Sequential Elements(con't...

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