lecture15 - Lecture 15: Sequential Elements (con't) EECS...

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EECS 312 1 Lecture 15: Sequential Elements (con’t) EECS 312 Reading: 7.1.1, 7.2-7.3.1 Exclude 7.2.4
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Clocked SR latch EECS 312 2 M 1 M 2 M 3 M 4 Q M 5 S M 6 CLK M 7 R M 8 CLK V DD Q Adding clock to synchronize This is not used in datapaths any more, but is a basic building memory cell (more on this later)
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Sizing Issues EECS 312 3 4.0 3.5 3.0 W/L 5 and 6 (a) 2.5 2.0 0.0 0.5 1.0 1.5 2.0 Q (Volts) time (ns) (b) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 1 2 W = 1 m µ 3 Volts Q S W = 0.9 m W = 0.8 m W = 0.7 m W = 0.6 m W = 0.5 m W/L 2 = 1.5 VTC Output voltage dependence on transistor width Transient response
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Timing Problems in Master-Slave EECS 312 4 φ φ φ φ D In A B φ φ Overlapping Clocks Can Cause • Race Conditions • Undefined Signals If overlap duration is longer than delay through 2 pass gates and 1 inverter, IN can propagate through to D falsely
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EECS 312 5 2-phase Dynamic Edge-triggered Register φ 2 φ 1 D In Input Sampled Output Enable φ 1 φ 2
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lecture15 - Lecture 15: Sequential Elements (con't) EECS...

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