lecture16 - Last Time Wrapped up sequential elements...

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EECS 312 1 Lecture 16: Memories (ROM) EECS 312 Reading: 12.1, 12.2.1, 12.2.2 EECS 312 2 Last Time • Wrapped up sequential elements – Schmitt triggers – Monostable circuits • Will delay BiCMOS lecture until after Midterm 2! EECS 312 3 Lecture Overview • Semiconductor memory introduction – Read-only memories (ROM) – Non-volatile read-write memories EECS 312 4 Semiconductor Memory Classification Key design metric: AREA Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM) FIFO Shift Register CAM LIFO
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EECS 312 5 General Memory Structure EECS 312 6 MOS NOR ROM WL [0] WL [1] WL [2] WL [3] BL [0] BL [1] BL [2] BL [3] GND GND V DD Pull-up devices N rows X M columns Each column looks like a pseudo-NMOS NOR gate Word Lines (WL) are default low Let WL[0] go high; this will pull down BL[1] Sizing determines VOL level EECS 312 7 MOS NOR ROM Programming Only 1 layer (contact mask) is used to program the memory array Transistors are present in every cell; contact is made if we want the transistor to operate (thus storing a 0) No contact Æ stores a 1 Programming of the memory can therefore be delayed to one of the last process steps Contacts take up a lot of area though EECS 312 8 MOS NAND ROM WL [0] WL [1] WL [2] WL [3] BL [0] BL
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lecture16 - Last Time Wrapped up sequential elements...

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