lecture18 - Last Time Lecture 18: Memories (DRAM) EECS 312...

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EECS 312 1 Lecture 18: Memories (DRAM) EECS 312 Reading: 12.2.3 EECS 312 2 Last Time • 6T SRAM cell is a key building block in digital design • Read and write processes are differentiated by how the bit lines are handled – Drive them to write new data into cell – Float and sense small changes to read EECS 312 3 Lecture Overview • Dynamic RAM – 1T cell operation – Memory trends EECS 312 4 Read-Write Memories (RAM) Recap • STATIC (SRAM) • DYNAMIC (DRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended
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EECS 312 5 1-Transistor DRAM Cell C S M 1 BL WL C BL WL X BL V DD V T V DD /2 V GND Write "1" Read "1" sensing V DD /2 VV V PRE –V BIT V PRE () C S C S C + ---------------- == Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance Voltage swing is small; typically around 250 mV.
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This note was uploaded on 04/01/2008 for the course EECS 312 taught by Professor Maharbiz during the Fall '07 term at University of Michigan.

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lecture18 - Last Time Lecture 18: Memories (DRAM) EECS 312...

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