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Unformatted text preview: 11/18/03 EECS 312 1 Lecture 19: Driving large capacitances EECS 312 Reading: 9.2.2 (pgs. 453-459), 5.4.3 (pgs. 207-210) 11/18/03 EECS 312 2 Lecture Overview Brief chip packaging overview to motivate: Driving large capacitive loads 11/18/03 EECS 312 3 Packaging Requirements Electrical: Low parasitics Mechanical: Reliable and Robust Thermal: Efficient Heat Removal Economical: Cheap 11/18/03 EECS 312 4 Bonding Techniques: Wirebonding Bond wires (~25 m) are used to connect the package to the chip Pads are arranged in a frame around the chip Pads are relatively large (~100 m in 0.25 m technology), with large pitch (200 m) Many chips areas are pad limited Lead Frame Substrate Die Pad 11/18/03 EECS 312 5 Flip-Chip Bonding Solder bumps Substrate Die Interconnect layers An alternative is flip-chip: Pads are distributed around the chip The solder bumps (lead-based) are placed on pads The chip is flipped onto the package Can have many more pads 11/18/03 EECS 312 6 Driving Large Capacitances ut t pHL = C L V swing /2 I av Transistor Sizing V in V out C L V DD 11/18/03 EECS 312 7 C L If C L is given:- How many stages are needed to minimize the delay?- How many stages are needed to minimize the delay?...
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This note was uploaded on 04/01/2008 for the course EECS 312 taught by Professor Maharbiz during the Fall '07 term at University of Michigan.
- Fall '07
- Integrated Circuit