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Unformatted text preview: It must prevent the instruction in the IF stage from committing its state. This means the instruction is neither allowed to write to the data memory nor the register file. 3. Consider the following instruction sequence: sub $2, $4, $5 beq $2, $3, somewhere Why doesn’t this code sequence work properly on this hardware (this is a bug in the book!)? This pipeline does not forward back to the ID stage. Therefore, the equal comparator won’t receive the updated value of register $2. 4. Can you fix this problem without adding hardware (i.e. only moving hardware around)? Explain. How many instructions must be “flushed” on a taken branch now? There are two possible answers to this question. You can either forward to the ID stage by putting muxes in front of the comparator, or you can move the comparator into the EXE stage. In the latter case, you would have to flush two instructions each time a branch is taken....
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This homework help was uploaded on 01/29/2008 for the course CS 152 taught by Professor Kubiatowicz during the Spring '04 term at Berkeley.
- Spring '04
- Computer Architecture