Computer Organization and Design: The Hardware/Software Interface

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CS152 Spring ‘03 Midterm II Page 1 University of California, Berkeley College of Engineering Computer Science Division EECS Spring 2003 John Kubiatowicz Midterm II SOLUTIONS May 7 th , 2003 CS152 Computer Architecture and Engineering Your Name: SID Number: Discussion Section: Problem Possible Score 1 20 2 25 3 30 4 25 Total
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CS152 Spring ‘03 Midterm II Page 3 Problem 1: Short Answers Problem 1a[2pts]: Give a simple definition of precise interrupts/exceptions. Why is this important? A precise interrupt or exception leaves the machine in a state for which there is a single instruction (PC) such that all instructions before that PC have committed their state and the instruction at the specified PC and all following instructions have not committed their state. This is important because it makes restarting the user program very simple. Problem 1b[3pts]: Explain why exceptions can occur out of order (in time) in an in-order, 5- stage pipeline. Give an example and explain how to achieve a precise exception point anyway. Exceptions can occur out of order because they can occur in different pipeline stages. For example, you could have a page-fault in the MEM stage of an early instruction after an illegal instruction fault in the DECODE stage of another: PC: F D E M W Fault in mem stage PC+4: F D E M W Fault in decode stage (earlier) Precise exceptions can be recovered by waiting until the M/W boundary to declare a fault. Problem 1c[3pts]: Name and define 3 types of pipeline data hazards. For each hazard, explain how it is prevented in the 5-stage pipeline: RAW: Read after Write hazard. This occurs if a later instruction reads a register from an earlier instruction while it is still in the pipeline. Fixed by forwarding. WAR: Write after read hazard. This occurs if a later instruction writes a register read by an earlier instruction before that instruction gets the old value. Fixed by the fact that the 5-stage pipeline executes in order and reads values early and writes them late. WAW: Write after Write hazard. This occurs if a later instruction writes a register written by an earlier instruction – and the result of the earlier instruction persists. Fixed by the fact that the 5- stage pipeline commits instructions in order.
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CS152 Spring ‘03 Midterm II Page 4 Problem 1d[2pts]: How do you refresh a DRAM, and why does this work (i.e. what is happening internally)? You refresh a DRAM by reading each ROW once every so often. This works because the DRAM reading process is restoring (the SENSE amps reinforce the values stored in the cells). Problem 1e[2pts]: What are load-delay slots? Does the programmer need to know about them (explain carefully): There are two options here. In non-stalling pipelines, the load-delay slots are the set of instructions following a load which cannot use the value of the load (because they will get the wrong value). In stalling pipelines, the load delay slots are the set of instructions following a load which will stall if they use the value of the load.
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