midterm1 solutions

Computer Organization and Design: The Hardware/Software Interface

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Spring 2003 John Kubiatowicz Midterm I March 12, 2003 CS152 Computer Architecture and Engineering Your Name: SID Number: Discussion Section: Problem Possible Score 1 25 2 20 3 25 4 30 Total
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2 [ This page left for π ] 3.141592653589793238462643383279502884197169399375105820974944
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3 Problem 1: Short Answer Problem 1a [3 pts]: What is Amdhal’s law? Give a formula and define the terms. How is this useful? Amdal’s law: speed up = n F F + - ) 1 ( 1 F is the part that you speed up n is the speed up ratio The Amdal’s law tells you can NOT speed up too much the whole system by speeding up only one part Problem 1b [3 pts]: What are setup and hold-time and how can they be violated in a synchronous circuit? Can you still use a chip that is experiencing hold-time violations? How about setup violations? T setup is the time that input signal should arrive before the clock edge T hold is the time that input signal should keep unchanged after the clock edge If the clock cycle time is not long enough, you could have Setup time violation. To avoid setup violation, the cycle time T clk should satisfy: T clk >T clk_Q +T max +T setup +T skew +T j If the combinational logic delay is too short, you could have hold time violation. The following has to be satisfied to avoid hold time violation: T clk_Q +T min >T skew +T hold If setup time is violated, you can slow down the clock to make the chip work If hold time is violated, you can NOT make the chip work Problem 1c [2 pts]: Is the multi-cycle data path always faster than the single-cycle data path? Explain. NO, for example: lw for MIPs in multi-cycle data path will be slower than single-cycle data path for more T clk_Q overhead is introduced in multi-cycle data path. Problem 1d [3 pts]: What are precise interrupts and why is it easy to provide them for our multi-cycle data path? Precise interrupts means that the instructions before offending instruction are executed but no instructions are executed after the offending instruction. In our multi-cycle data path, it is easy to provide precise interrupts for interrupts only occur before WB stage and instructions are executed in order.
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4 Problem 1e [3 pts]: Suppose that you have analyzed a benchmark that runs on your company’s processor. This processor runs at 500MHz and has the following characteristics: Instruction Type Frequency (%) Cycles Arithmetic and logical 40 1 Load and Store 30 2 Branches 20 1 Floating Point 10 12 What is the CPI and MIPS rating of this processor running this benchmark? CPI=1*0.4+2*0.30+1*0.2+12*0.10= 2.4 MIPS=500/2.4= 208 MIPS Problem 1f [2 pts]: What is the technique used for a carry-select adder and how can it be used in general to speed up hardware ( hint: this is a very general technique to make a time space tradeoff ) In carry select adder, you pre-compute the addition both with carry in “0” and “1”. Then, the correct result is selected by the late arrival carry in. In general, you can throw in more hardware, do parallel pre-computing and select the correct by using late arrival signal, which can speed up the hardware.
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This homework help was uploaded on 01/29/2008 for the course CS 152 taught by Professor Kubiatowicz during the Spring '04 term at Berkeley.

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midterm1 solutions - University of California, Berkeley...

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