Modified ch8.ppt - Chapter 8 Main Memory Operating System Concepts – 9th Edition Silberschatz Galvin and Gagne ©2013 Chapter 8 Memory Management

Modified ch8.ppt - Chapter 8 Main Memory Operating System...

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Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Chapter 8: Main Memory
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8.2 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Chapter 8: Memory Management Background Swapping Contiguous Memory Allocation Segmentation Paging Structure of the Page Table Example: The Intel 32 and 64-bit Architectures Example: ARM Architecture
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8.3 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Objectives To provide a detailed description of various ways of organizing memory hardware To discuss various memory-management techniques, including paging and segmentation To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with paging
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8.4 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Background Program must be brought (from disk) into memory and placed within a process for it to be run Main memory and registers are only storage CPU can access directly Memory unit only sees a stream of addresses + read requests, or address + data and write requests Register access in one CPU clock (or less) Main memory can take many cycles, causing a stall Cache sits between main memory and CPU registers Protection of memory required to ensure correct operation
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8.5 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Base and Limit Registers A pair of base and limit registers define the logical address space CPU must check every memory access generated in user mode to be sure it is between base and limit for that user
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8.6 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Hardware Address Protection
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8.7 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Address Binding Programs on disk, ready to be brought into memory to execute form an input queue Without support, must be loaded into address 0000 Inconvenient to have first user process physical address always at 0000 How can it not be? Further, addresses represented in different ways at different stages of a program’ s life Source code addresses usually symbolic Compiled code addresses bind to relocatable addresses i.e. “ 14 bytes from beginning of this module Linker or loader will bind relocatable addresses to absolute addresses i.e. 74014 Each binding maps one address space to another
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8.8 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Binding of Instructions and Data to Memory Address binding of instructions and data to memory addresses can happen at three different stages Compile time : If memory location known a priori, absolute code can be generated; must recompile code if starting location changes Load time : Must generate relocatable code if memory location is not known at compile time Execution time : Binding delayed until run time if the process
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