Computer Organization and Design: The Hardware/Software Interface

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CS152 Spring ‘03 Midterm II Page 1 University of California, Berkeley College of Engineering Computer Science Division EECS Spring 2003 John Kubiatowicz Midterm II May 7 th , 2003 CS152 Computer Architecture and Engineering Your Name: SID Number: Discussion Section: Problem Possible Score 1 20 2 25 3 30 4 25 Total
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CS152 Spring ‘03 Midterm II Page 3 Problem 1: Short Answers Problem 1a[2pts]: Give a simple definition of precise interrupts/exceptions. Why is this important? Problem 1b[3pts]: Explain why exceptions can occur out of order (in time) in an in-order, 5- stage pipeline. Give an example and explain how to achieve a precise exception point anyway. Problem 1c[3pts]: Name and define 3 types of pipeline data hazards. For each hazard, explain how it is prevented in the 5-stage pipeline:
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CS152 Spring ‘03 Midterm II Page 4 Problem 1d[2pts]: How do you refresh a DRAM, and why does this work (i.e. what is happening internally)? Problem 1e[2pts]: What are load-delay slots? Does the programmer need to know about them (explain carefully): Problem 1f[2pts]: Why is it important for Tomasulo to issue instructions in-order?
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CS152 Spring ‘03 Midterm II Page 5 Problem 1g[2pts]: What is a victim cache? What is it good for? Problem 1h[2pts]: Name and describe the structure that permits an out-of-order processor to achieve precise interrupts. How does this work? Problem 1i[2pts]: Suppose you have a processor with a 4K page size, 16K first-level data cache with 128-bit cache lines. Assume that you want to overlap TLB lookup with cache lookup. What is the required associativity of the first-level cache?
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CS152 Spring ‘03 Midterm II Page 7 Problem 2: Memory Hierarchy Problem 2a[2pts]: Assume that we have a byte-addressed 64-bit processor with 64-bit words. Suppose that this processor has a 48-word, three-way, set-associative cache (LRU replacement) with 2-word cache lines. Split the 64-bit address into “tag”, “index”, and “cache-line offset” pieces. Which address bits comprise each piece (one is given)? tag: index: cache-line offset: bits 3 – 0 Problem 2b[2pts]: How many sets does this cache have? Explain. Problem 2c[7pts]: Assume that the processor makes the following byte accesses. Label each reference address as a Hit (H) or a Miss (M). Also, identify each cache miss as a compulsory, conflict, or capacity miss. Byte Address Hit/Miss? Miss Type 38(0x026) Miss Compulsory 172(0x0AC) 144(0x090) 85(0x055) 424(0x1A8) 111(0x06F) 174(0x0AE) 551(0x227) 90(0x05A) 32(0x020) 428(0x1AC) 544(0x220) 96(0x060) 422(0x1A6) 170(0x0AA) Problem 2d[2pts]: Calculate the cache hit rate (you can leave as a fraction).
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