Computer Organization and Design: The Hardware/Software Interface

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Spring 2003 John Kubiatowicz Midterm I March 12, 2003 CS152 Computer Architecture and Engineering Your Name: SID Number: Discussion Section: Problem Possible Score 1 25 2 20 3 25 4 30 Total
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2 [ This page left for π ] 3.141592653589793238462643383279502884197169399375105820974944
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3 Problem 1: Short Answer Problem 1a [3 pts]: What is Amdhal’s law? Give a formula and define the terms. How is this useful? Problem 1b [3 pts]: What are setup and hold-time and how can they be violated in a synchronous circuit? Can you still use a chip that is experiencing hold-time violations? How about setup violations? Problem 1c [2 pts]: Is the multi-cycle data path always faster than the single-cycle data path? Explain. Problem 1d [3 pts]: What are precise interrupts and why is it easy to provide them for our multi-cycle data path?
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4 Problem 1e [3 pts]: Suppose that you have analyzed a benchmark that runs on your company’s processor. This processor runs at 500MHz and has the following characteristics: Instruction Type Frequency (%) Cycles Arithmetic and logical 40 1 Load and Store 30 2 Branches 20 1 Floating Point 10 12 What is the CPI and MIPS rating of this processor running this benchmark? Problem 1f [2 pts]: What is the technique used for a carry-select adder and how can it be used in general to speed up hardware ( hint: this is a very general technique to make a time space tradeoff ) Problem 1g [3pts]: What does it mean for a branch to have a delay slot, and why does it complicate the servicing of interrupts?
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5 Problem 1h[3pts]: The Clark paper on testing talked about using randomness in at least two different ways during testing of the VAX. What were they? Problem 1i [3 pts]: The 1-bit Booth algorithm recodes one of the operands of a multiplier from binary into trinary logic with symbols: 1 , 0, and 1. The transformation occurs one bit at a time, as given in class: Suppose we encode 3 bits at a time. Finish filling out the following transformation table: Cur Prev Out 0 0 0 0 1 1 1 0 1 1 1 0 Cur Prev Out 000 0 0 000 1 1 001 0 1 001 1 2 010 0 010 1 011 0 011 1 100 0 100 1 101 0 101 1 110 0 110 1 111 0 111 1
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6 Problem 2: Delay For a Full Adder A key component of an ALU is a full adder. A symbol for a full adder is: Problem 2a [5pts]: Implement a full adder using as few 2-input AND, OR, and XOR gates as possible. Keep in mind that the Carry In signal may arrive much later than the A or B inputs. Thus, optimize your design (if possible) to have as few gates between Carry In and the two outputs as possible: Full Adder A B S C in C out
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7 Assume the following characteristics for the gates: AND: Input load: 100fF, Propagation delay: TPlh=0.4ns, TPhl=0.4ns, Load-Dependent delay: TPlhf=.0020ns, TPhlf=.0021ns OR: Input load: 100fF Propagation delay: TPlh=0.2ns, TPhl=0.6ns Load-Dependent delay: TPlhf=.0020ns, TPhlf=.0021ns XOR: Input load: 200fF, Propagation delay: TPlh=.8ns, TPhl=.8ns
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This homework help was uploaded on 01/29/2008 for the course CS 152 taught by Professor Kubiatowicz during the Spring '04 term at University of California, Berkeley.

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Sp03 midterm 1 - University of California, Berkeley College...

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