Computer Organization and Design: The Hardware/Software Interface

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1 University of California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz Homework Quiz (HW #6) SOLUTIONS November 10, 1999 CS152 Computer Architecture and Engineering This quiz combines two of the problems from homework #6. Good Luck! Your Name: SID Number: Discussion Section: Total:
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3 Cache organization Your company has an application that must be run as fast as possible. The hardware division of your company has come up with three separate first-level cache configurations: Machine I: Direct-mapped with one-word blocks Machine II: Direct-mapped with four-word blocks Machine III: Two-way set associative with four-word blocks For each of these machines, the cache fill penalty is 6 cycles + 1 cycle for each word. You did some experiments and measured the following instruction mix for the application: Branch: 20%, Load: 13%, Store: 12%, Float Insts: 20%, Integer: 35% Further, through a hardware cache monitor, you measured the following miss rates:
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fa99 homequiz 6 solution - University of California,...

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