Lab 2 - BME 303 Spring 2007 BME 303 Lab Assignment#2 MM...

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BME 303 Spring 2007 BME 303 Lab Assignment #2 – MM Logic Intro. This lab will count as one HW assignment. Complete each section in class and demonstrate it to your TA. If you do not finish it during the scheduled lab session, complete it on your own, and demonstrate it to your TA at the beginning of the next lab session. Exercise 1 (25%) Implement the 3-to-8 decoder and create a truth table for the response of your circuit. An example of a 2- to-4 decoder is shown in the figure below. A B C Out1 Out2 Out3 Out4 Out5 Out6 Out7 Out8 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 Exercise 2 (25%) Implement a 4-to-1 MUX and create a truth table for the response of your circuit. A schematic of a 4-to1 MUX is shown in the figure below. S=1 S=2 Output 1 1 Dependent on Switch A 1 0 Dependent on Switch B 0 1 Dependent on Switch C 0 0 Dependent on Switch D **NOTE: The full truth table would be 64 lines long and unnecessary. This table demonstrates the basic concept.
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BME 303 Spring 2007 Exercise 3 (25%) Implement a full adder using a programmable logic array (PLA). Hint: you can modify the 3-to-8 decoder from Exercise 1.
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