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Unformatted text preview: Transistor-Transistor Logic (TTL) and Other TTL Gates Contents Transistor-Transistor Logic (TTL) Transistor-Transistor Logic (TTL) and Other TTL Gates Basic TTL Inverter Basic TTL NAND Gate Standard TTL NAND Gate TTL Fan-Out Open-Collector TTL Low Power TTL (LTTL) High Speed TTL (HTTL) Other TTL Gates AND Gate NOR Gate OR Gate AND-OR-INVERT (AOI) Gates XOR Gate Schmitt Trigger Inverters and NAND Gates Transistor-Transistor Logic (TTL) which is introduced in 1965 in order to provide increased fan-out, improved transient response and reduced chip area. A basic TTL inverter and its VTC are shown in the gure on the left and right above, respectively. Compare the TTL inverter with the DTL inverter in order to see how diodes DI and DL are represented by the base-emitter and base-collector junctions of the input transistor QI which replaced these two diodes. Basic Emitter-Coupled Schmitt Trigger Noninverter Schmitt Trigger NAND Gate Tri-State Buers Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 1 / 49 Basic TTL Inverter (while VIN < VIH ) As QO is in cuto mode when VIN = 0 V, the output is HIGH as VOU T = VCC . When the input voltage is high enough, i.e., VIN = VBE(F A) − VCE(SAT ) , QO goes into the forward active (FA) mode and current IRC will start to ow. Then, VOU T starts to drop with increasing VIN as VOU T = VCC − IRC RC . If we increase VIN further, at some point (i.e., when VIN = VBE(SAT ) − VCE(SAT ) ), QO goes into saturation and QI goes into reverse-active mode. As a result, VOU T becomes LOW and remains constant at VOU T = VCE,O(SAT ) . Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates When the input is low, e.g., VIN = 0 V, base-emitter junction of QI is forward biased, however voltage at the base of QI is not enough to turn on both base-collector junction of QI and base-emitter junction of QO , so QO is cuto. So, collector current of QI is zero, i.e., IC,I = 0. Thus, QI is in saturation mode (as IC < βF IB ). VBE,O = VIN + VCE,I(SAT ) Basic TTL Inverter 09-Dec-2017 3 / 49 Basic TTL Inverter 09-Dec-2017 2 / 49 Basic TTL Inverter We can summarize the state of the active elements for output-high and output-low states as indicated in the table below. State of Active Elements for Output-High and Output-Low States Element QO QI VOH VOL Cuto (OFF) Saturated (SAT) Saturated (SAT) Reverse Active (RA) Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 4 / 49 Basic TTL NAND Gate Basic TTL NAND Gate NAND function is inherently provided by the TTL logic family by using a multiple-emitter BJT (ensuring a much-less chip area) as shown in the gure below for a three-input basic TTL NAND gate. Thus, VOH = VCC VOL = VCE,O(SAT ) VIL = VBE,O(F A) − VCE,I(SAT ) VIH = VBE,O(SAT ) − VCE,I(SAT ) Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II 09-Dec-2017 5 / 49 Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II 09-Dec-2017 6 / 49 Transistor-Transistor Logic (TTL) and Other TTL Gates Standard TTL NAND Gate Transistor-Transistor Logic (TTL) and Other TTL Gates Standard TTL NAND Gate Standard TTL NAND Gate Basic TTL inverter can be improved by adding a totem-pole output (stacking of two BJTs, a resistor and diode in the output branch) to provide active pull-up and pull-down sections, a drive-splitter transistor QS , a discharge resistor RD and clamping diodes at the inputs as shown in the gure on the left above. The purpose of each element in the circuit is listed in the table on the right above. Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 7 / 49 Standard TTL NAND Gate ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 9 / 49 Standard TTL NAND Gate State of Active Elements for Output-High and Output-Low States QO QS QI QP DL VOH Cuto (OFF) Cuto (OFF) Saturated (SAT) Edge of conduction (EOC) Edge of conduction (EOC) Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) VOB Edge of conduction (EOC) Forward active (FA) Saturated (SAT) Edge of conduction (EOC) Edge of conduction (EOC) ELE315 Electronics II = VCC − VBE,P (F A) − VD,L(ON ) Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II 09-Dec-2017 8 / 49 Standard TTL NAND Gate If VIN is kept increasing, then at some point (i.e., when VIN = VBE,O(SAT ) + VBE,S(SAT ) − VCE,I(SAT ) ), both QS and QO go into the saturation mode, QP goes into cuto mode and QI goes into the reverse-active mode. As a result, VOU T becomes LOW and remains constant at VOU T = VCE,O(SAT ) . Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates The states of active elements in a standard TTL inverter are given in the table below. Element VOU T = VCC − IRC(OH) RC − VBE,P (EOC) − VD,L(EOC) Transistor-Transistor Logic (TTL) and Other TTL Gates When the input voltage is high enough, i.e., VIN = VBE,S(F A) − VCE,I(SAT ) , QS goes into the forward active (FA) mode and current IRC will start to ow. Then, VOU T starts to drop with increasing VIN as VOU T = VCC − IRC RC − VBE,P (EOC) − VD,L(EOC) . If we increase VIN further, then at some point (i.e., when VIN = VBE,O(F A) + VBE,S(F A) − VCE,I(SAT ) ), QO turns into forward active mode. As a result, VOU T decreases more rapidly as IC,O also starts to ow and more current starts to ow from RC . This point is called the break point. The input and output voltages at the break point are labelled as VIB and VOB , respectively. Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) When the input is low, e.g., VIN = 0 V, base-emitter junction of QI is forward biased, however voltage at the base of QI is not enough to turn on both base-collector junction of QI and base-emitter junction of QS , so QS and QO are cuto. So, collector current of QI is zero and QI is in saturation mode. When VIN = 0 V, QS and QO are in cuto mode and QP is in edge-of-conduction (EOC) mode (i.e., no current ows as there is no-load). So, as IRC(OH) = IB,P (EOC) = 0, the output is HIGH and given as Thus, 09-Dec-2017 10 / 49 Standard TTL NAND Gate VOH = VCC − VBE,P (F A) − VD,L(ON ) VOB = VCC − IC,S(F A) RC − VBE,P (F A) − VD,L(ON ) VOL Saturated (SAT) Saturated (SAT) Reverse active (RA) Cuto (OFF) Cuto (OFF) 09-Dec-2017 11 / 49 = VCC − VBE,O(F A) RD RC − VBE,P (F A) − VD,L(ON ) VOL = VCE,O(SAT ) VIL = VBE,S(F A) − VCE,I(SAT ) VIB = VBE,O(F A) + VBE,S(F A) − VCE,I(SAT ) VIH = VBE,O(SAT ) + VBE,S(SAT ) − VCE,I(SAT ) Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II 09-Dec-2017 12 / 49 Transistor-Transistor Logic (TTL) and Other TTL Gates Standard TTL NAND Gate Transistor-Transistor Logic (TTL) and Other TTL Gates TTL Fan-Out TTL Fan-Out Example 1: For the TTL gate above, determine the VTC critical points VOH , VOL , VIL , VIH , VIB and VOB for βF = 100 and σmax = 0.85. Maximum fan-out will be determined by the output-low state, as when output is high 0 input transistor Q0I is in reverse active mode (i.e., IIH = 0). From Path 1, IOL = I −I =I C,O(SAT ) Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 13 / 49 TTL Fan-Out Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 14 / 49 TTL Fan-Out IB,S(SAT ) = IC,I(RA) IB,O(SAT ) = IE,S(SAT ) − IRD(OL) = (1 + βR )IB,I(RA) VBE,O(SAT ) RD IB,I(RA) = IE,S(SAT ) = IC,S(SAT ) + IB,S(SAT ) IC,S(SAT ) = C,O(SAT ) From Path 3, Continuing IRD(OL) = D,L(EOC) IC,O(SAT ) = σβF IB,O(SAT ) Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II VCC − VCE,S(SAT ) − VBE,O(SAT ) Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates From Path 1, (from Path 2) RC 09-Dec-2017 VCC − VBC,I(RA) − VBE,S(SAT ) − VBE,O(SAT ) 0 IIL = 15 / 49 TTL Fan-Out RB VCC − VBE,I(SAT ) − VCE,O(SAT ) RB Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 16 / 49 TTL Fan-Out Thus, the maximum fan-out is given by $ Nmax = IOL(max) 0 IIL $ = Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) % $ = IC,O(SAT )(max) σmax βF IB,O(SAT ) 0 IIL Example 2: For the TTL gate above, determine the maximum fan-out for βF % βR = 0.1 0 IIL = 25, TTL Power Dissipation % ELE315 Electronics II and σmax = 0.85. Example 3: Calculate the average power dissipation for Example 2 above? 09-Dec-2017 17 / 49 Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II 09-Dec-2017 18 / 49 Transistor-Transistor Logic (TTL) and Other TTL Gates Open-Collector TTL Transistor-Transistor Logic (TTL) and Other TTL Gates Open-Collector TTL Low Power TTL (LTTL) Open-collector TTL gates, one of which is shown in the gure above, are often used in data busses where multiple gate outputs must be ANDed. This can be accomplished by using a single pull-up resistor with open-collector TTL gates. This type of connection is referred to as wired-AND. Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) Low Power TTL (LTTL) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 19 / 49 Low Power TTL (LTTL) Power dissipation can be lowered by just increasing the resistance values as shown in the gure above. However, this results in: decreased fan-out, longer transient response times. Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 20 / 49 High Speed TTL (HTTL) High Speed TTL (HTTL) Example 4: Calculate the average power dissipation for LTTL in the gure above and compare it with that of TTL which was calculated in Example 3. Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 21 / 49 Other TTL Gates Switching speed can be increased by just decreasing the resistance values as shown in the gure above. An additional Darlington pair is also used to improve the low-to-high switching speed, together with REP resistor which provides a discharge path for QP 2 in order to improve the high-to-low switching speed. However, this results in increased power dissipation. Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates Other TTL Gates 09-Dec-2017 22 / 49 AND Gate AND Gate NAND gate will become an AND date, if the output drivers are enabled in the inverse fashion. This is accomplished by using an inverting driver splitter as shown in the block diagram of the gure below. In this section, we are going to investigate the following TTL gates AND gates NOR gates OR gates AND-OR-INVERT (AOI) gates This second level inversion is accomplished by QS2 , QSD , DS , RSD and RCS which are enclosed in the shaded block in the gure on the left below. XOR gates Schmitt Trigger Inverters and NAND gates Tri-State buers Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II 09-Dec-2017 23 / 49 Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II 09-Dec-2017 24 / 49 Transistor-Transistor Logic (TTL) and Other TTL Gates AND Gate Transistor-Transistor Logic (TTL) and Other TTL Gates When the input is low, e.g., VIN = 0 V, QI is saturated, QS2 and QSD are cuto. Consequently, QS and QO are saturated, and QP and DL are cuto. So, the output is LOW, i.e., VOL = VCE,O(SAT ) . The output will start increase when QO goes from saturation mode to forward active mode. Only QS2 being in forward active mode is not enough to decrease the voltage at the base of QS below 1.6 V and change the state of QO . So, QSD needs to go into forward active mode as well. Thus, the value of the input to make the output rise is equal to VIL = VBE,SD(F A) + VBE,S2(F A) − VCE,I(SAT ) . QS will turn o when the voltage at its base goes below 0.7 V and this will occur suddenly when QSD and QS2 go into saturation. Thus, the value of the input which makes the output high is given by VIH = VBE,SD(SAT ) + VBE,S2(SAT ) − VCE,I(SAT ) . Then, QI goes into reverse active mode and the output stays high. Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 25 / 49 AND Gate AND Gate The states of active elements in a standard TTL noninverter are given in the table below. Element QO QS QP DL QSD QS2 DS QI State of Active Elements for Output-High and Output-Low States VOL Saturated (SAT) Saturated (SAT) Cuto (OFF) Cuto (OFF) Cuto (OFF) Cuto (OFF) Conducting (ON) Saturated (SAT) Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) VOH Cuto (OFF) Cuto (OFF) Edge of conduction (EOC) Edge of conduction (EOC) Saturated (SAT) Saturated (SAT) Conducting (ON) Reverse active (RA) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 26 / 49 NOR Gate NOR Gate NOR function is obtained by using separate input sections QI , RB and QS for the inputs where drive splitter transistors are connected in parallel (i.e., their collectors and emitters are connected together) as shown in the gure on the left below. Circuit symbol for the NOR gate is also displayed in the gure on the right below. A knee is not present in the VTC of the TTL AND gate in contrast to the VTC of the TTL NAND gate, and the transition region is more abrupt. Thus, VOL = VCE,O(SAT ) VOH = VCC − VBE,P (F A) − VD,L(ON ) VIL = VBE,SD(F A) + VBE,S2(F A) − VCE,I(SAT ) VIH = VBE,SD(SAT ) + VBE,S2(SAT ) − VCE,I(SAT ) Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 27 / 49 NOR Gate Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 28 / 49 OR Gate OR Gate OR function is obtained by using separate input sections and parallel drive splitter transistors of the second lvel inversion circuitry as shown in the gure on the left below. Circuit symbol for the OR gate is also displayed in the gure on the right below. Example 5: For the two input TTL NOR gate above, determine the average power dissipation and compare the result with that of a standard TTL inverter calculated in Example 3. NOTE: You need to consider all four possible input states. Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II 09-Dec-2017 29 / 49 Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II 09-Dec-2017 30 / 49 Transistor-Transistor Logic (TTL) and Other TTL Gates AND-OR-INVERT (AOI) Gates Transistor-Transistor Logic (TTL) and Other TTL Gates AND-OR-INVERT (AOI) Gates TTL gates performing more complex logic functions can be designed using the following rules AND-OR-INVERT (AOI) Gates Example 6: Design a four-input AOI TTL gate which performs VOU T Solution: = VA VB + VC VD . 1. ANDing of signals Multi-emitter input BJT sections 2. ORing of signals Multiple input sections (QI and RB ) Multiple and parallel connected drive splitting BJTs (QS ) 3. If non-inverting ORing is desired Additional logic inversion circuitry with parallel connected drive splitting BJTs 4. Totem-pole output branch Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 31 / 49 AND-OR-INVERT (AOI) Gates Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates Example 8: Design a six-input AOI TTL gate which performs Solution: Solution: Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 32 / 49 09-Dec-2017 34 / 49 AND-OR-INVERT (AOI) Gates Example 7: Design a six-input AOI TTL gate which performs VOU T = VA VB + VC + VD VE VF . 09-Dec-2017 VOU T = VA VB + VC + VD VE VF . 09-Dec-2017 33 / 49 XOR Gate Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates XOR Gate XOR Gate We can form an XORing logic pair using two transistors: by connecting one input to the base of the rst transistor and to the emitter of the second transistor, and connecting the other input to the base of the second transistor and to the emitter of the rst transistor where the collectors of the transistors are connected together, as shown in the gure below. Circuit symbol and truth table for an XOR gate are given in the gure above and the table below, respectively. Truth Table for an XOR Gate VIN A LOW LOW HIGH HIGH VIN B LOW HIGH LOW HIGH VOU T LOW HIGH HIGH LOW As we notice, the output is LOW when the inputs are the same, and HIGH when the inputs are dierent. Also, the outputs will be the same, even when the inputs are inverted, i.e, F =A⊕B =A⊕B Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II 09-Dec-2017 35 / 49 Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II 09-Dec-2017 36 / 49 Transistor-Transistor Logic (TTL) and Other TTL Gates Schmitt Trigger Inverters and NAND Gates Transistor-Transistor Logic (TTL) and Other TTL Gates Schmitt Trigger Inverters and NAND Gates Consider a noisy signal, shown at the top of the gure on the left below, as an input to an inverter gate. We need to produce a neat inverter output signal considering the input is LOW before t2 , HIGH between t2 and t3 , LOW between t5 and t8 and HIGH after t8 , as shown at the bottom of the gure on the left below. Schmitt Trigger Inverters and NAND Gates Basic Emitter-Coupled Schmitt Trigger Noninverter Hysteresis can be achieved by the basic emitter-coupled noninverting Schmitt Trigger circuit shown in the gure on the left above. As seen from the gure on the right above, VTC exhibits hysteresis, i.e., low-to-high path is not the same as the high-to-low path of the input-output relationship. Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 37 / 49 Schmitt Trigger Inverters and NAND Gates Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II 09-Dec-2017 38 / 49 Schmitt Trigger Inverters and NAND Gates Thus, VIU S is given by  VE = VCC − VBE,S2(SAT ) RCS1 + VCC − VCE,S2(SAT ) RCS2   Req VIU S = where Req = RCS1 ||RCS2 ||RSE . Thus, VOLS is given by  VCC − VE − VBE,S2(SAT ) VCC − VE − VCE,S2(SAT ) VE = + RSE RCS1 RCS2 Transistor-Transistor Logic (TTL) and Other TTL Gates We nd VE as VOLS = Let us rst investigate, low-to-high path of the input. When input is LOW, e.g., VIN S = 0 V, then QS1 is cuto and QS2 is in saturation. Thus, the output is LOW, i.e., VOU T S = VOLS = VE + VCE,S2(SAT ) . So, IE,S2 = IB,S2 + IC,S2 , i.e., VCC − VBE,S2(SAT ) RCS1 + VCC − VCE,S2(SAT ) RCS2  Req + VCE,S2(SAT ) ELE315 Electronics II Transistor-Transistor Logic (TTL) and Other TTL Gates 09-Dec-2017 39 / 49 Schmitt Trigger Inverters and NAND Gates VCC − VBE,S2(F A) RCS1 /RSE + 1 Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE315 Electronics II 09-Dec-2017 40 / 49 Schmitt Trigger Inverters and NAND Gates Example 9: For the Schmitt Trigger noninverter circuit above, determine the VOHS , VOLS , VIU S and VIDS values where RCS1 = 4 kΩ, RCS2 = 2.5 kΩ, and RSE = 1 kΩ. = 606 Ω, VOHS = 5 V   VCC − VBE,S2(SAT ) VCC − VCE,S2(SAT ) VE,S2(SAT ) = + Req = 1.8 V RCS1 RCS2 VOLS = VE,S2(SAT ) + VCE,S2(SAT ) = 2 V VIU S = VE,S2(SAT ) + VBE,S1(F A) = 2.5 V + VBE,S1(SAT ) ELE315 Electronics II Re...
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