EE2000-Lab4.pdf - City University of Hong Kong Department of Electronic Engineering EE 2000 – Lab Manual 4 4 to 2 Priority Encoder design Course

EE2000-Lab4.pdf - City University of Hong Kong Department...

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1 City University of Hong Kong Department of Electronic Engineering EE 2000 – Lab Manual 4 4 to 2 Priority Encoder design Course Leader: Dr. Ricky LAU and Dr. Ray C.C. CHEUNG
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2 Objectives: Implement a 4 to 2 priority encoder using VHDL. Implement a latched output for the priority encoder using VHDL. Experiment 1: 4 to 2 priority encoder implementation 1. Implement a 4 to 2 encoder i. A priority encoder is a circuit that compresses multiple binary inputs into a smaller number of outputs. It is a typical example of combinational logic circuits. The output of a priority encoder is the binary representation of the original number starting from zero of the most significant input bit. They are often used to control interrupt requests. The truth table and logic gates schematic of a 4 to 2 priority encoder is shown as below. S(3) S(2) S(1) S(0) en O(0) O(1) V S(3) S(2) S(1) S(0) en O(1) O(0) V - - - - 0 Z Z 0 0 0 0 1 1 0 0 1 0 0 1 - 1 0 1 1 0 1 - - 1 1 0 1 1 - - - 1 1 1 0 0 0 0 1 Z Z 0 ii. Create a new project and create a new VHDL source file “encoder_4to2.vhd” to a new project. Based on the truth table, you can use IF-THEN-ELSE statement inside a process to describe the behavior of the 4 to 2 priority encoder. A template is given as follows:
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